Search results: tag:"hdl coder" - MATLAB Answers

899 questions found in Answers

Results 51 - 100 of 899

1

answer

0 votes
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Specify the Location of custom IP cores in HDL Coder

Asked by John on 2 Apr 2025

Latest activity Answered by Walter Roberson on 2 Apr 2025

Code Generation

1

answer

0 votes
7 views

Implementing parallel processing and handling sampling vs. clock rate differences in an OFDM system using Simulink, HDL Coder, AXI Interface.

Asked by Jina on 2 Apr 2025

Latest activity Answered by Jack on 2 Apr 2025

Accepted Answer by Jack

FPGA, ASIC, and SoC Development Wireless HDL Toolbox HDL-Optimized System Design

1

answer

0 votes
2 views

HDLCoder RAM mapping not working

Asked by Amogh on 1 Apr 2025

Latest activity Answered by Ryan Baird on 1 Apr 2025

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

0

answers

0 votes
5 views

HDL Workflow Advisor -- Error Connecting to SSH Server

Asked by Ezenia on 25 Feb 2025

Latest activity Edited by Justin on 31 Mar 2025

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

2

answers

0 votes
3 views

HDL Coder; Matlab Function Blocks and Clocked Processes

Asked by Florian Rössing on 16 Aug 2024

Latest activity Edited by Sahas on 17 Mar 2025

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

2

answers

0 votes
3 views

Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？

Asked by Conglin Pan on 15 Mar 2022

Latest activity Edited by Kiran Kintali on 13 Mar 2025

Code Generation

2

answers

0 votes
12 views

HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing

Asked by Dario on 6 Mar 2025

Latest activity Commented on by Dario on 11 Mar 2025

Code Generation HDL Coder Get Started with HDL Coder

0

answers

0 votes
2 views

HDL Coder and Bitstream Programming Insight Needed

Asked by Thomas J Kelly on 23 Aug 2024

Latest activity Commented on by Sahas on 11 Mar 2025

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
10 views

Simulink HDL Coder error when generating

Asked by Mikel on 20 Feb 2025

Latest activity Commented on by Steven Hatcher on 6 Mar 2025

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

0

answers

0 votes
0 views

HDL Workflow Advisor error when programming target device -- Invalid argument at position 3. Value must be text with one or more characters

Asked by Ezenia on 25 Feb 2025

Latest activity Edited by Sahas on 4 Mar 2025

Code Generation HDL Coder HDL Code Generation from Simulink Programmatic Workflow

1

answer

0 votes
1 view

Code generation does not support display for handle classes. 'comm.HDLRSEncoder' is a handle class.

Asked by Maryem Hamdi on 14 Jan 2021

Latest activity Answered by Umeshraja on 4 Mar 2025

Code Generation HDL Coder HDL Code Generation from MATLAB External Component Interfaces

1

answer

0 votes
2 views

How to configure number of CORDIC iterations used in Real Divide HDL Optimized Block?

Asked by Urvish on 26 Feb 2025

Latest activity Commented on by Urvish on 28 Feb 2025

Accepted Answer by Divyajyoti Nayak

Code Generation Fixed-Point Designer Embedded Implementation Fixed-Point Math Operations in MATLAB and Simulink

0

answers

0 votes
2 views

Build Linux Image for HDL Coder

Asked by John on 24 Feb 2025

Latest activity Commented on by John on 24 Feb 2025

Code Generation

1

answer

1 vote
22 views

How do I configure HDL Coder so that it recognizes my Vivado version?

Asked by Ezenia on 18 Feb 2025

Latest activity Commented on by Ezenia on 24 Feb 2025

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

0

answers

0 votes
3 views

HDL Coder Support Package for Intel FPGA and SoC Devices Setup

Asked by John on 7 Feb 2025

Latest activity Edited by John on 21 Feb 2025

Code Generation HDL Coder

0

answers

0 votes
2 views

Use Conduit Interface in HDL Coder

Asked by John on 20 Feb 2025

Code Generation

1

answer

0 votes
3 views

Assistance Required: Warning during Simscape HDL Workflow Advisor Conversion Process

Asked by Minkwang Lee on 10 Feb 2025

Latest activity Edited by Aabha on 13 Feb 2025

Accepted Answer by Aabha

Physical Modeling Simscape Real-Time Simulation Real-Time Deployment and Code Generation

2

answers

0 votes
2 views

HDL Coder Variable Size Matrix

Asked by Caner KOREL on 17 Nov 2022

Latest activity Commented on by Hau on 13 Feb 2025

Accepted Answer by Ryan Baird

Signal Processing DSP System Toolbox Code Generation HDL Code Generation

1

answer

0 votes
13 views

MATLAB HDL-Coder: Expression could not be reduced to a constant.

Asked by Gregor on 10 Feb 2025

Latest activity Answered by Kiran Kintali on 10 Feb 2025

Accepted Answer by Kiran Kintali

Code Generation

1

answer

0 votes
4 views

Specify clock pins in HDL Reference Design

Asked by John on 28 Jan 2025

Latest activity Commented on by Angela Cuadros Castiblanco on 30 Jan 2025

Accepted Answer by Angela Cuadros Castiblanco

Code Generation HDL Coder HDL Code Generation from MATLAB Speed and Area Optimization

3

answers

2 votes
9 views

what is the difference between FPGA Turnkey and IP Core Generation?

Asked by Yashar on 7 Aug 2015

Latest activity Edited by Kiran Kintali on 13 Jan 2025

Accepted Answer by Wang Chen

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
1 view

Purpose of software loopback in IO334_ad_da_hdlc.slx Model for Speedgoat IO334 Analog Interface.

Asked by Klemen D on 10 Jan 2025

Latest activity Commented on by Klemen D on 13 Jan 2025

Accepted Answer by Dimitri MANKOV

Physical Modeling Simscape Real-Time Simulation Real-Time Deployment and Code Generation

2

answers

0 votes
9 views

How to add TCL script to HDL Coder IP Core generation

Asked by Alex Aronov on 15 Sep 2023

Latest activity Edited by Kiran Kintali on 7 Jan 2025

Accepted Answer by Wang Chen

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
3 views

How to get digital/analog input to speedgoat processor using IO334-325k

Asked by Yeung Pok Nga on 20 Dec 2024

Latest activity Commented on by Yeung Pok Nga on 7 Jan 2025

Code Generation

2

answers

0 votes
5 views

Is it possible to integrate the HDL CODE generated by simulink into an existing user-defined vivado project?

Asked by xiaojie on 29 Dec 2024

Latest activity Answered by Kiran Kintali on 31 Dec 2024

Accepted Answer by Arjun

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

2

answers

0 votes
1 view

Find Sample Code: "HDL Coder Release Notes: Improvements to delay balancing"

Asked by 恩慈 on 16 Dec 2024

Latest activity Answered by Winston Lin on 26 Dec 2024

Accepted Answer by Winston Lin

Code Generation

1

answer

0 votes
4 views

Bitstream Generated through HDL workflow advisor

Asked by Rimsha Javed on 16 May 2023

Latest activity Answered by Sahas on 19 Dec 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

0

answers

0 votes
0 views

Mathworks ipcore test using axi4stream in linux

Asked by El Hachimi on 17 Dec 2024

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

DSP HDL Coder - NCO mixed types error

Asked by Mark on 5 Nov 2024

Latest activity Edited by Githin George on 2 Dec 2024

Signal Processing DSP System Toolbox Code Generation HDL Code Generation

1

answer

0 votes
3 views

HDL Coder "Error using find Too many input arguments."

Asked by Richard on 28 Nov 2024

Latest activity Answered by Kiran Kintali on 1 Dec 2024

Code Generation

1

answer

0 votes
3 views

Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?

Asked by xiaodong yu on 19 Nov 2024

Latest activity Commented on by Steven Hatcher on 20 Nov 2024

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
23 views

Verilog Code generation for my ONNX Model

Asked by ATHUL on 25 Oct 2024

Latest activity Edited by Manikanta Aditya on 13 Nov 2024

Code Generation Embedded Coder Deployment, Integration, and Supported Hardware Embedded Coder Supported Hardware Intel SoC Devices

1

answer

0 votes
3 views

Give initial value to the "AXI4 Random Access Memory" block in simulink

Asked by ALi Falahati on 1 Feb 2023

Latest activity Edited by Govind KM on 7 Nov 2024

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
5 views

HDL Coder Vivado timing report shows infinite slack

Asked by Yeung Pok Nga on 2 May 2024

Latest activity Answered by Shlok on 30 Oct 2024

Code Generation

1

answer

0 votes
7 views

How to convert ARINC429 model into HDL Code

Asked by Shubham on 24 Oct 2024

Latest activity Answered by R on 25 Oct 2024

Code Generation HDL Coder HDL Coder Supported Hardware Intel FPGA and SoC Devices

1

answer

0 votes
3 views

FPGA Synthesis and Analysis HDL Coder

Asked by Shubham on 18 Oct 2024

Latest activity Answered by Sahas on 21 Oct 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
5 views

How to resolve the exceed of maximum supported wordlength of 128 bits in hdlcoder?

Asked by kim lee on 22 Aug 2018

Latest activity Commented on by Xisheng Yu on 15 Oct 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design Native Floating Point

1

answer

0 votes
7 views

How do I interface the GPIOs on zedboard?

Asked by Vallabh on 26 Sep 2024

Latest activity Edited by Sameer Mule on 9 Oct 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
7 views

How to connect a zybo Z7 20 to the Simulink using FPGA in the loop

Asked by Oussama on 24 Sep 2024

Latest activity Moved by Walter Roberson on 8 Oct 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
4 views

Characterisation error in HDL code generation?

Asked by Dylan on 6 Oct 2024

Latest activity Commented on by Steven Hatcher on 7 Oct 2024

Code Generation

3

answers

1 vote
9 views

struct memeber can not be Simulink.Parameter?

Asked by dayu lai on 29 Jul 2021

Latest activity Answered by Shivam Malviya on 13 Sep 2024

Accepted Answer by Shivam Malviya

Code Generation

1

answer

0 votes
3 views

generated rs code function result is not different with matlab simulink simulation

Asked by heo on 10 Sep 2024

Latest activity Answered by Kiran Kintali on 10 Sep 2024

Code Generation HDL Coder

1

answer

0 votes
1 view

How to properly use hdl.RAM for Matlab to VHDL conversion?

Asked by Rubén on 6 Sep 2024

Latest activity Commented on by Jacob Mazur on 9 Sep 2024

Code Generation HDL Coder

0

answers

0 votes
0 views

hdlset_param question

Asked by GLW on 25 Jul 2024

Latest activity Edited by Umar on 2 Aug 2024

Code Generation HDL Coder Get Started with HDL Coder

0

answers

0 votes
1 view

How do we get the linux device driver files matlab/hdl coder generatwes for the ipcore we made in matlab?

Asked by ivan on 29 Jul 2024

Latest activity Commented on by Umar on 29 Jul 2024

Code Generation HDL Coder HDL Coder Supported Hardware AMD FPGA and SoC Devices

1

answer

0 votes
3 views

Unable to see FFT output in co-simulation after HDL conversion.

Asked by Jaykishan Solanki on 8 Jul 2024

Latest activity Edited by akshatsood on 15 Jul 2024

FPGA, ASIC, and SoC Development

1

answer

0 votes
1 view

Unable to see fft output during co-simulation.

Asked by Jaykishan Solanki on 9 Jul 2024

Latest activity Answered by Sahas on 11 Jul 2024

Accepted Answer by Sahas

MATLAB

1

answer

0 votes
5 views

Fixed-point conversion error of dsphdl.FFT

Asked by Jaykishan Solanki on 9 Jul 2024

Latest activity Answered by Manikanta Aditya on 9 Jul 2024

Accepted Answer by Manikanta Aditya

FPGA, ASIC, and SoC Development DSP HDL Toolbox HDL-Optimized Filters and Transforms

1

answer

0 votes
1 view

Call graph generation from VHDL code files.

Asked by Jaykishan Solanki on 29 Jun 2024

Latest activity Edited by Kiran Kintali on 8 Jul 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Verifier

1

answer

0 votes
0 views

Can't understand individual VHDL files generated.

Asked by Jaykishan Solanki on 5 Jul 2024

Latest activity Answered by Aditya on 5 Jul 2024

Accepted Answer by Aditya

Code Generation HDL Coder Get Started with HDL Coder

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