Questions tagged [simulation]
About tools to simulate circuits. Specify the tool used.
2,173 questions
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Modeling RF Impedance Matching PCB Geometry
I am designing RF amplifiers, and I often use LDMOS transistors with unmatched inputs and outputs. My goal is to learn how to model and simulate PCB impedance-matching geometry on a computer before ...
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Effective resistance of a finite grid of resistor
I have computed the equivalent resistance between two opposite vertices of a square grid of resistor using just the rule for series/parallel. I found many discussions on these, but cannot find a ...
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LTSpice: Zener diode breaks .op analysis?
I have a problem with .op analysis in LTSpice. Below you can see a part of an audio amplifier I'm tinkering with. For most of the time, I just simply used a voltage source instead of a zener diode. I ...
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Simulating and understanding an old circuit board from old electric vehicle (NGGSPICE)
I have been recently working on a really old electric vehicle and going through all electronics to understand how it works. I stumbled across this rather weird analogue circuit which uses comparators ...
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LTspice simulation results of current programmed mode control for buck converter not matching one shown in the book
I'm trying to simulate the Current Programmed Mode Control subcircuit for the buck converter described in section 18.5 of the Book Fundamentals of Power Electronics by Dragan Maksimović and Erickson, ...
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Order of series RLC components - same circuit, different values
I'm learning about series RLC and I want to ask a question/confirm my theory on what's happening in the circuit.
I want to ask about the order in the RLC, the only difference between the circuits are ...
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Stepper Motor Control Circuit in Multisim (74193 + 74LS04 + 74LS08 + QBD139) —> LEDs Not Lighting
I’m working on a stepper motor control circuit in Multisim using the following ICs:
74193 (4-bit binary counter)
74LS04 (inverter)
74LS08 (AND gate)
QBD139 (NPN-Transistor)
The goal is to simulate a ...
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Error Simulating ESP32 in Proteus
I'm using Proteus 9.1 I'm running into trouble simulating a ESP32. From what I know, it should be working.
The python file
...
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In a seven segment display, why does my "6" looks like a small letter "b"
I have made this circuit on Proteus, a simple BCD to 7-segment display:
But the segments for 6 and 9 are not completely lit. What could be the potential reasons? The decoder IC is CD4511 and a common ...
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LC tank resonance in LTSPICE
I am simulating a lossless LC tank driven by an AC source in LTSpice. The source frequency is the same as the tank's resonant frequency. I expect to see the inductor current and capacitor voltage grow ...
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How do I simulate the RDS value in LTspice?
I'm having trouble finding any material, for example: a manual or video that shows how to measure the RDS of a MOSFET in LTSpice.I want to understand the behavior in this circuit I've built.
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Confusion with transient analysis and initial condidtions in LTSPice
While I was measuring various things in this amplifier design so I could understand it better, I tried to use a square wave as a source signal. I used pulse voltage source, specified parameters and ...
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Will the TLV7031 low-voltage comparator work with this input voltage?
Since I have not worked with low power currents in the uA range before, I would like to ask you before starting the design. I have simulated the circuit below and have a few questions about it.
When ...
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LT Spice: Why does my SCR act like a Diode in 3 ph converter simulation
I am learning LT Spice. As you can see from the waveform a lot of things are going wrong here.
The green waveform indicates gate pulse of SCR U1, blue waveform indicates anode-cathode voltage across ...
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JK flip flop behavior on startup in Verilog
I've tried to implement a JK flip flop in Verilog, but while testing, I found that whatever inputs of j and k I give on startup, until I reset the flip flop (j=0, k=1), the outputs will not be seen ...
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Noise Results from Transient Noise Simulation and Noise Simulation
I am analyzing the noise performance of a simple RC circuit in the 20 Hz - 20 kHz band. The schematic is shown below:
I have used two different methods to simulate noise in order to compare the ...
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Simulate induced voltage in PCB loop because of a second loop that is fed by a given voltage signal waveform
I fear that might be too broad but for educational experiments, I would like to know as specifically as possible how to simulate the induced voltage in a PCB loop (let´s call it Loop 1) as an effect/...
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How to modify resistor value to achieve -10°C offset in Perry TITE301/MC thermostat circuit?
I’m modifying a Perry TITE301/MC thermostat to change the temperature offset applied when the remote control is activated.
By default, activating the remote (closing contacts 6 and 7) lowers the ...
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Why is the waveform not matching? (2 clock delay in FSM code)
Context : I have been tasked with testing a HC-04 Ultrasonic sensor with Verilog, and below is the Verilog code, the testbench and the waveform that I am getting,
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meas directive has issues with expressions and parameters [ngspice]
In a netlist being simulated using ngspice, why do the following expressions evaluate to different results:
...
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What am I doing wrong in LTSpice v24.1.9 regarding measure and parameter statements?
.meas TRAN hey AVG V(V_Load) FROM 0 TO 100
.param stop=(hey<120)?1:0
.param base_cup=0.5
.param cup1={0.401*stop}
...
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Proteus won't simulate my RC circuits (low-pass and high-pass filters)
I have a bigger project where I need this two signals, a ramp and a pulse. Basically, one that starts at 0V and goes up to approximately 5V and stays there, and another one that does the opposite (...
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LTspice battery simulation (need >100 W sink capability) – grammatical error with Q={Ceff()*x}
I’m trying to simulate a cell in LTspice to test charging and sinking >100 W into a pack. I picked up a behavioral model (based on Chen & Rincón-Mora's work, OCV vs SOC + RC networks - github ...
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Generate PSPICE OLB from Lib (SMBJ3V3)
I am trying to create a PSPICE library using Vishay's .Lib. I have managed to do this, but unfortunately the library is still faulty. I took a look at the Lib file and discovered SPICE parameters that ...
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153
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How to fix .op spice directive not working but .trans spice directive working in ltspice simulation for a buck converter?
To illustrate the design of PI and PD compensators, Fundamentals of Power Electronics by Robert Erickson and Dragan Maksimovic book considers the design of a combined
PID compensator for the DC–DC ...
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162
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Unused Port Error in LTSpice averaged circuit model simulation and unknown extra terms in Spice netlist
I'm trying to reproduce a simulation of the SEPIC CCM averaged circuit model using LTspice from the SPICE netlist provided by the author of the book Fundamentals of Power Electronics by Robert W. ...
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130
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How to translate a netlist to schematic for simulating averaged switch model in LTSpice
I’m trying to reproduce an averaged switch model from Fundamentals of Power Electronics (Erickson & Maksimović) in LTspice. The book defines the subcircuit as:
...
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Trying to do both synthesis and simulation for iCE40 UP5K when using internal clock and LED driver, but can only get one or the other [closed]
Before putting in an order for an Upduino to take another stab at learning about FPGAs, I figured I'd get the toolchain (yosys and nextpnr) figured out first and work through some tutorials. This was ...
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Interpreting Negative Input Impedance
I would like to accurately simulate a basic CE amplifier that I have soldered and probed with a 10 MHz sine wave applied to the input.
My amplifier Zin simulations yield a negative resistive component ...
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Thermal equivalent circuit simulation
I have built-up an thermal equivalent circuit and want to simulate it with LTSpice.
It worked very good until I added some features.
I don't understand why the voltage makes a jump in the beginning of ...
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2
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LTSpice Diodes Inc. Schottky Diode Spice Model Question
I'm trying to simulate this simple LDO circuit but I'm having trouble adding my schottky diode BAT750 from Diodes Inc. into the simulation.
I kept getting this error
and I'm suspecting it's because ...
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Why isn't inductor current remaining same in the following circuit at time t=0?
I am trying to understand inductor behaviour, specifically boosting action provided by them by means of the following circuit.
Initially switch SW2 is closed and SW1 is open.
I expect inductor ...
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91
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COMSOL Simulation Too Slow Due to Fine Mesh in Local Region. How to Improve Performance?
I’m running into an issue with long meshing and simulation times in COMSOL, likely due to the scale differences of my model. I’m simulating an electric field interacting with a thin film that’s 120 nm ...
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Class A Amplifier - Theory v. Simulation
I am trying to compare theoretical results with the simulation of the following amplifier.
The respective values are
$$V_\mathrm{CC} = 12\,\text{V}, R_\mathrm{B} = 470\,\text{k}\Omega, R_\mathrm{C} = ...
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Capacitor charge with 1A and followed by -1A
I have a capacitor in parallel of a resistance (R=1 Ohm and C=1F) and I want to simulate the capacitor voltage on excel. I apply for 3s (step 0.1s) 1A. At 3.1s, I change the current to -1A.
Until 3s, ...
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152
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LTSpice op-amp non-inverting input acts like pull-up
I've been trying to analyze an op-amp non-inverting amplifier with LMH6629 with LTSpice using the PSPice file from official Texas Instruments site (
https://www.ti.com/product/LMH6629#design-tools-...
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How to generate N bits from integer parameter in LTSpice
What would be an efficient way to generate N bits (nets with voltage 0 or v_high) from an integer parameter?
I tried to make a subcircuit that I can evoke with a .param like ...
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Moving beyond static field approximation for modeling high-current micro-scale plasma discharge
my background knowledge : a second year student electrical engineering and computer science ,
I’m working on understanding the magnetic field generated by a very small and fast transient system used ...
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99
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Why is the waveform this way when attempting to simulate a full-wave bridge rectifier in Altium?
I was trying to simulate a full wave bridge rectifier in Altium Designer. But I don't know why the input wave is coming like that.
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25 kHz signal amplifier using op-amp
So I have this schematic to drive a transducer load from op-amp at 25 kHz (ultrasonic sound). The problem is, all I do is simulating it using LTSpice but I can't find the final result even though my ...
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AND gate giving error, but shouldn't?
I'm new to logisim evolution and really logic circuits in general. Why does the AND gate at the end give an error? When switch 1 is off it doesn't give an error. When the controlled buffers are ...
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LTspice - Make a single simulation with multiple user defined component
I'm quite new on LTspice, and I wonder If it's possible to make a simulation of multiple user defined component (.asy files) without modify the schematic.
I have this circuit and I would like to ...
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148
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Why this common emitter BJT not creating a zero at desired frequency?
I am trying to simulate a circuit, and I want to amplify the frequency at 350MHz and above and I want to attenuate the lower frequencies below 350MHz
I have created this circuit, which, in my ...
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Analyzing unexpected output from Verilog bit unpacking and reassembly logic
I'm working on a Verilog task that rearranges bits from a 312-bit word into a new 312-bit format using 8-bit temporary storage (temp[39]). Below is a simplified ...
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Designing a power amplifier using BJT
I have a question about designing a power amplifier, and I don't know how to match the different stages together!
Question: Replace the first stage by folded-cascode and any current source by current ...
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126
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Floating node in LTspice
I have a question about designing power amplifier.
Question: Find the current of the current source I3.
My solution: I supposed that the Vbe of Q1 is 0.6v and with Is=10^(-14) calculated the Ic1, ...
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LTspice String DAC switching with .STEP
I want to simulate a 7 decade string DAC in LTspice for linearity and worst case, but I get the error message below. The type of simulation is operation point. The yellow rectangles are 2-pole rotary ...
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When simulating the open loop gain of an oscillator in LTspice, what to use as output load?
I have an LTspice circuit of a Colpitts oscillator with an common emitter amplifier:
I'm using dual value resistors (R6 and R7) so that the circuit is a closed loop in transient and DC simulation and ...
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Why is the simulation failing in SIMPLIS?
I'm still working on designing my push-pull converter, for which I’ve already managed to determine the open-loop transfer function in this question:
How can I measure the transfer function of a push-...
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How blocking assignment affect non-blocking assignment in Verilog?
module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule
Output of above Verilog code is:
...
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