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answer

0 votes
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code c generation in matlab

Asked by mohsen salehi on 28 Nov 2017

Latest activity Commented on by mehmet on 20 Mar 2025

Code Generation HDL Coder Targeting FPGA & SoC Hardware

4

answers

0 votes
7 views

Problem with the Connecttion between Zybo Z7 20 and Matlab

Asked by Li Qian on 1 Aug 2018

Latest activity Edited by 佳禹 on 16 Sep 2023

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
9 views

To what degree are MathWorks drivers and libraries involved in the new ADI libiio based Linux images for Zynq + AD9361 targets?

Asked by Terje Olsen on 4 Dec 2019

Latest activity Commented on by Rimsha Javed on 7 Jun 2023

Accepted Answer by Ousman Sadiq

Code Generation HDL Coder Targeting FPGA & SoC Hardware

Find Documentation, Examples and more on Targeting FPGA & SoC Hardware in Help Center

1

answer

0 votes
1 view

Introduce Zybo board in Simulink HDL coder workflow advisor

Asked by Juan Valverde on 6 Jul 2015

Latest activity Answered by Kiran Kintali on 6 Mar 2023

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
2 views

Is it possible to create a custom board for the HDL Coder with the zynq z7100

Asked by Patrick Ebner on 30 Oct 2017

Latest activity Edited by Stefanie Schwarz on 29 Jun 2022

Accepted Answer by Wang Chen

Code Generation HDL Coder Targeting FPGA & SoC Hardware

2

answers

0 votes
17 views

Communication from processor (PS) to the FPGA (PL) via AXI4-lite

Asked by Quoc Viet Bui on 15 Jan 2020

Latest activity Answered by Steve Kuznicki on 26 Apr 2022

Accepted Answer by Steve Kuznicki

Code Generation HDL Coder Targeting FPGA & SoC Hardware

Find Code on Targeting FPGA & SoC Hardware in File Exchange

1

answer

0 votes
6 views

Hardware Software Co-design support for ZCU111

Asked by Aunullah Qaiser on 26 Feb 2020

Latest activity Commented on by Kefayet Ullah on 14 Apr 2022

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

Can I get a list of Altera FPGA boards supported by matlab/simulink?

Asked by VINAL PATEL on 16 Sep 2016

Latest activity Commented on by SimTec on 26 Jan 2022

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
9 views

DE-10 Nano development kit

Asked by Nawaf Hassan on 5 Oct 2020

Latest activity Answered by Kiran Kintali on 24 Oct 2020

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
2 views

How to use genetic xilinx platform in HDL coder.

Asked by Suphadet Vatjanajaroenrat on 7 Sep 2018

Latest activity Answered by Kiran Kintali on 20 Oct 2020

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
7 views

DE-10 Nano development kit

Asked by Nawaf Hassan on 2 Oct 2020

Latest activity Answered by Kiran Kintali on 2 Oct 2020

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

Custom Convolution neural network model code conversion for FPGA

Asked by Ali Shahid on 24 Sep 2020

Latest activity Answered by Kiran Kintali on 24 Sep 2020

Code Generation HDL Coder Targeting FPGA & SoC Hardware

2

answers

0 votes
1 view

Is Deep Learning HDL Toolbox supports Xilinx All Programmable 7000 ZC702 board?

Asked by TURIMERLA PRATAP on 20 Sep 2020

Latest activity Commented on by stozaki on 20 Sep 2020

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
3 views

HDL Coder - Generate IP Core with Vivado 2015

Asked by Zachary Blair on 11 Jan 2016

Latest activity Commented on by kheddara rania on 10 Jul 2020

Code Generation HDL Coder Targeting FPGA & SoC Hardware Generate IP Core and Bitstream

3

answers

1 vote
7 views

Not able to connect zynq7010 to MATLAB

Asked by TARIQ ABDUL RAHMAN on 19 Mar 2019

Latest activity Answered by Stefanie Schwarz on 17 Jul 2019

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
0 views

Getting Started with Hardware-Software Co-Design Workflow for Intel SoC Devices

Asked by Vipin Venugopal on 15 Apr 2019

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
9 views

hw/sw Co-Design Workflow and UDP communication between Zynq zedboard and host computer

Asked by imane RGUIB on 26 Feb 2019

Latest activity Edited by Steve Kuznicki on 28 Feb 2019

Accepted Answer by Steve Kuznicki

Code Generation HDL Coder Targeting FPGA & SoC Hardware

3

answers

0 votes
6 views

Chang center frequency quickly

Asked by Ardeal Liang on 24 Oct 2018

Latest activity Commented on by Paul on 6 Nov 2018

Accepted Answer by Ardeal Liang

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
4 views

How to control GPIO of ARM on Zedboard

Asked by Ardeal Liang on 25 Oct 2018

Latest activity Commented on by Ardeal Liang on 6 Nov 2018

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
2 views

Why does Simulink default to LCC Compiler instead of using Xilinx SDK toolchain and how do I correct the tool chain?

Asked by William Katzianer on 5 Nov 2018

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
2 views

[Zynq ad9361 fmscomms2 qpsk co-design] How to increase the sampling rate

Asked by hoang viet on 6 Oct 2017

Latest activity Commented on by Saqib Ali on 13 Apr 2018

Code Generation HDL Coder Targeting FPGA & SoC Hardware

2

answers

0 votes
7 views

ADALM-PLUTO Radio Hardware Software Co-Design

Asked by Adeel on 8 Apr 2018

Latest activity Commented on by Noam Levine on 13 Apr 2018

Accepted Answer by Adeel

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
0 views

Problem with 'Fine Frequency Compensation' in HW/SW QPSK transceiver using FMCOMMS1

Asked by hoang viet on 6 Feb 2018

Latest activity Edited by Noam Levine on 12 Apr 2018

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

1 vote
0 views

Setup Linux® on the Xilinx Zynq hardware platform

Asked by Anirudh Acharya on 3 Nov 2016

Latest activity Commented on by Anirudh Acharya on 5 Nov 2017

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
6 views

HW/SW Co-design full deployment using ZedBoard issues

Asked by J. Smith on 16 Jun 2016

Latest activity Commented on by Jan on 6 Jul 2017

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
7 views

Getting Started with Hardware-Software Codesign Workflow for Xilinx Zynq Platform - BUG

Asked by Jean Jacques on 2 May 2016

Latest activity Answered by Tim McBrayer on 2 May 2016

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
10 views

How do I deploy an ARM software executable from a Simulink model to my Zynq board to run in standalone mode? And how can this exectuable be auto-run on startup?

Asked by MathWorks Support Team on 30 Jul 2019

Latest activity Edited by MathWorks Support Team on 24 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
1 view

How to add AXI UART IP to ADRV9361-Z7035 in HW/SW Co-Design

Asked by Takuji Ebinuma on 9 Oct 2022

Latest activity Commented on by Rahul Barnwal on 10 Oct 2023

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
5 views

adi rf som gpio options

Asked by Raz Elimelech on 3 Dec 2023

Latest activity Commented on by Raz Elimelech on 6 Dec 2023

Accepted Answer by Tom Richter

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
1 view

ZED board clock speed

Asked by Mike Bardill on 20 May 2016

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
0 views

How to send more data through UDP in HW/SW Co-Design

Asked by MaksymHolub99 on 10 Jun 2020

Latest activity Answered by MaksymHolub99 on 25 Jun 2020

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
18 views

HW/SW Co-Design with AXI4-Stream Using analog device ADRV9002

Asked by Arash Jafari on 6 Mar 2022

Latest activity Edited by Arash Jafari on 7 Mar 2022

Accepted Answer by Noam Levine

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
1 view

How to select the data source in example "HWSW Co-Design QPSK Transmit and Receive Using Analog Devices AD9361AD9364"

Asked by 晓晓刘 on 16 May 2021

Latest activity Answered by Jieming Xu on 18 May 2021

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
16 views

Change RF parameters from matlab using libiio on adrv9361z7035

Asked by aeon jose on 8 Jul 2021

Latest activity Edited by aeon jose on 3 Aug 2021

Accepted Answer by Martin Enderwitz

Code Generation HDL Coder Targeting FPGA & SoC Hardware

2

answers

0 votes
38 views

I am getting the error: make command return an error of 2, while trying to implement a software interface model of OFDM Transmit and Receive Using Analog Devices AD9361/AD9364

Asked by Vedansh Garg on 16 Dec 2022

Latest activity Answered by Bhanu Medasani on 14 Nov 2025 at 12:59

Accepted Answer by Harshit Gupta

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
12 views

Integrating HDL QPSK Transmitter and Receiver into Xilinx Vivado

Asked by jonjon on 24 Jul 2023

Latest activity Answered by Kiran Kintali on 6 Oct 2023

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
17 views

How can I create a custom Linux image for my custom board to use the Zynq workflow or Intel SoC workflow with MATLAB/Simulink?

Asked by MathWorks Support Team on 17 Jul 2021

Latest activity Edited by MathWorks Support Team on 8 Apr 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
0 views

Mathworks ipcore test using axi4stream in linux

Asked by El Hachimi on 17 Dec 2024

Code Generation HDL Coder Targeting FPGA & SoC Hardware

0

answers

0 votes
1 view

HDL workflow advisor error during step "4.1: Create Project"

Asked by maged ahmed on 3 Mar 2022

Code Generation HDL Coder Targeting FPGA & SoC Hardware

2

answers

0 votes
3 views

ZedBoard support package in a different module

Asked by Antti Wredfors on 9 Sep 2016

Latest activity Commented on by Antoine Bostem on 18 Sep 2018

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
1 view

Why do IP repositories for HW/SW Co-design fail to be found?

Asked by MathWorks Support Team on 6 Apr 2020

Latest activity Edited by MathWorks Support Team on 1 Apr 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

3

answers

0 votes
6 views

Multiple outputs from HDL block in simulink

Asked by muhammad ahmad on 29 Oct 2021

Latest activity Commented on by JT Ferrara on 2 Nov 2021

Accepted Answer by JT Ferrara

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
0 views

Matlab, Simulink, Xilinx, FPGA ----> Hardware in the loop

Asked by Jean on 7 Nov 2011

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
2 views

Can't register a custom board for the HDL Deep Learning Toolbox

Asked by Andrés on 19 Feb 2025

Latest activity Commented on by Vikram Venkatesh on 5 Mar 2025

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
6 views

Deep Learning HDL Toolbox with CycloneV SoC board

Asked by Rubén on 13 May 2025

Latest activity Answered by Kiran Kintali on 27 May 2025

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
37 views

How to configure host interface and setup scripts for FPGA I/O?

Asked by Sergei on 29 Oct 2025

Latest activity Commented on by Sergei on 5 Nov 2025 at 10:52

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
6 views

How do I use unsupported synthesis tool versions with Deep Learning HDL Toolbox?

Asked by MathWorks Support Team on 5 Oct 2023

Latest activity Edited by MathWorks Support Team on 19 Feb 2025

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

2

answers

0 votes
5 views

zcu102 executable not really run when launched from command line

Asked by TuttoAlDoc on 18 Aug 2025

Latest activity Edited by Adit on 1 Sep 2025

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

3 votes
4 views

IP core generation fails with vivado error

Asked by Bence on 6 Nov 2015

Latest activity Edited by Kiran Kintali on 29 Oct 2023

Accepted Answer by Kiran Kintali

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
7 views

Are Digilent Zybo boards supported for the Zynq workflow with HDL Coder & Embedded Coder?

Asked by MathWorks Support Team on 20 Apr 2022

Latest activity Edited by MathWorks Support Team on 31 Mar 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

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