3

I'm used to writing code in VHDL in emacs, which has the nice beautify functionality that will align signal assignments. Is there something similar with the Verilog Mode?

Convert this:

r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

To This:

r_Tx_Done     <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main   <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

Verilog mode does a good job keeping if else begin end aligned, but it doesn't align assignments like I want. Note that inside the if statement doesn't align to <= outside the if statement. Essentially I want each begin/end block treated separately.

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2
  • 1
    There doesn't seem to be an automatic alignment feature, but you can use align-regexp manually, as described in this question. Commented Jul 1, 2014 at 16:52
  • 1
    That works for small sections of code, but for a large file that would be extremely tedious to align everything manually. Commented Jul 1, 2014 at 17:18

3 Answers 3

Reset to default
6

I use verilog mode, and I have found this works by default.

  1. Type C-x h to highlight the entire buffer.
  2. Then TAB to get it to beautify everything. Much easier and less tedious!
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2

Based on this answer you can try to customize align-rules-list.

Something like this should help:

(eval-after-load "align"
  '(add-to-list 'align-rules-list
                '(verilog-assignment
                  (regexp . "\\(\\s-*\\)<=")
                  (mode   . '(verilog-mode))
                  (repeat . nil))))

Now M-x align should apply the new alignment rule.

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4 Comments

I tried adding that to my .emacs file and got this message: Warning (initialization): An error occurred while loading `c:/emacs/.emacs': Symbol's value as variable is void: align-rules-list
@Russell, it sounds like you hadn't loaded align yet. Try the update snippet in my answer.
this solution is pretty good, but it doesn't quite behave exactly the way I would like. If my code has nested if-else statements it pushes everything to the furthest one out, which adds quite a bit of whitespace in some situations. I'll keep the question open for a bit longer before I accept it as an answer to see if anyone has any other suggestions.
@Russell, it might help if you add your more detailed use case to your question.
2

In Verilog mode for GNU Emacs 24.3.1 you can place the cursor on the non-blocking assignment operator "<=" in any of the assignment operations. For instance, in the top portion of the code:

r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;

place the cursor on either of the assignment operators and type C-c =. The code will now become 

r_Tx_Done     <= 1'b1;
r_Clock_Count <= 0;

This operation will only be performed in that section of code. This operation will not jump into any other statements: if-else, case, always, etc. In order to perform the same operation in another statement you would have to go inside that statement click on an assignment operator and type C-c = again.

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