Does SystemVerilog enables aliases for module instances and enumerations? Eg, how could I code this:
enum logic {foo, bar} myEnum
enum logic {baz, qux} myEnum
ie, baz and qux are aliases of foo and bar respectively.
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2 Answers
The let construct can do this for any expression
enum logic {foo, bar} myEnum
let baz = foo;
let qux = bar;
You cannot alias an instance name.
Comments
They cannot be aliased, but the can be casted/converted. Refer to IEEE Std 1800-2012 § 6.19.4 Enumerated types in numerical expressions. Example for the LRM:
typedef enum {Red, Green, Blue} Colors; typedef enum {Mo,Tu,We,Th,Fr,Sa,Su} Week; Colors C; Week W; int I; C = Colors'(C+1); // C is converted to an integer, then added to // one, then converted back to a Colors type C = C + 1; C++; C+=2; C = I; // Illegal because they would all be // assignments of expressions without a cast C = Colors'(Su); // Legal; puts an out of range value into C I = C + W; // Legal; C and W are automatically cast to int
