How to map a single bit of a signal to multiple bits of a Vector?

Question

I've tried to map a bit of a signal (here addS of type signed(32 downto 0)) in a structural description like this:

add2 : entity work.adderSigned(behavioral) 
  generic map(N => 64)
    port map(a(63 downto 32) => mulssS, --concat 
        a(31 downto 0) => signed(muluuS), --concat
     -- b(63 downto 48) => addS(32 downto 32),
        b(63 downto 48) => (others => addS(32)), --the critical line
        b(47 downto 16) => addS(31 downto 0),
        b(15 downto 0) => (others => '0'),
        std_logic_vector(y) => y);

but the compiler complains that this isn't a static mapping. How can I perform this mapping?

Simpler : specify the range statically. b(63 downto 48) => (63 downto 48 => addS(32)), — user1818839
– user1818839, Commented Nov 29, 2015 at 19:24
(others => ???) should work as long as a and b are constrained vectors. What tool do you use? Some tools don't support the evaluation of complex expressions on the right hand side of a port assignment (like signed (...)). — Paebbels
– Paebbels, Commented Nov 29, 2015 at 22:50
I use ModelSim and I think a is constrained through the N generic. a is declared as a : in std_logic_vector(N-1 downto 0) — Sebi2020
– Sebi2020, Commented Nov 29, 2015 at 23:26

Morten Zilmer · Accepted Answer · 2015-11-30 07:43:00Z

1

In VHDL-2008 the line b(63 downto 48) => (others => addS(32)), is valid, so enable VHDL-2008 if the tool allows.

For VHDL-2002, if an expression is used as actual (right side in port map), then it must be a globally static expression (VHDL-2002 1.1.1.2 Ports), but (others => addS(32)) ain't, since addS(32) is not static. A work around can be:

signal b_63_dt_48 : std_logic_vector(63 downto 48);
...
b(63 downto 48) => b_63_dt_48,
...
b_63_dt_48 <= (others => addS(32));

Btw. looks like there may be some odd about the line std_logic_vector(y) => y.

edited Nov 30, 2015 at 7:43

answered Nov 29, 2015 at 19:13

Morten Zilmer

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3 Comments

Sebi2020 Over a year ago

i want to convert the signal data (signed integer) to a std_logic_vector... isn't this the way to achieve that? VHDL doesn't complain about this line (ModelSim)

Sebi2020 Over a year ago

It's a task I've got and it's not allowed to implement it in a behavioural way or to change build commands.

Martin Zabel Over a year ago

@Sebi2020 What is actually not allowed to change? The ports of the entity adderSigned (left-hand side of port map) or the signal assignments in the code snipped (right-hand side of port map)?

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