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I have a custom (soft, 16 bit) RISC architecture for which I want Clang to generate LLVM IR.

How much of a backend do I need to create in order to generate IR for the custom architecture. i.e. infinite registers and LLVM types in IR, no assembly language output, no machine code generation.

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You have to add tiny piece of code into Clang to register new architecture and its main features, such as word size (16 bit in your case), preferred alignment for all llvm types (i1, i8, i16, i32 etc.). You can find similar code in the Clang source tree for the MSP430 architecture, for example. After you add this code for your target, Clang can generate IR code for this target.

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