ModelSim Altera 10.1d - verilog I can't get wave forms

Question

I have a basic bistable code, i compile it without any errors, but when i whant to add waveforms after i hit run(f9), my altera program doesn't do anything... Here is my code:

module bistable(input a, 
            input rst, 
            input ck,
            output reg out);
always@(posedge ck) 
if(!rst) out<=0; 
   else out<=a;         
endmodule

Test module:

module test();
reg a; 
reg ck; 
reg rst; 
wire out; 
bistable bis(.a(a),.ck(ck),.rst(rst),.out(out));

initial begin
ck=0;
forever ck=~ck;
end
initial begin
a=1;
rst=0;
#14 rst=1;
#20 rst=0;
#10;
$stop;
end
endmodule

I did programs without clock and my waveforms appeared very well, but that's not what I think is the cause of my problem.

Thanks in advance for any help!

Greg · Accepted Answer · 2017-05-22 18:01:23Z

0

forever ck=~ck; is a zero time infinite loop. The simulation will not move to the next time step until all operations on the current time step is completed (which is impossible when there is a zero time infinite loop).

Adding time delay to your clock will help. For example: forever #5 ck=~ck;

Check your log file. Some simulators will report errors or warnings when they encounter an infinite loop.

answered May 22, 2017 at 18:01

Greg

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