VHDL Generic component declaration syntax error

Question

I am having a simple generic single clock ram, and it has multiple generic values. However, I am getting a syntax error while declaring it. The full structure of the code is:

entity main is
Port ( 
-- components
);
end main;


architecture Behavioral of main is
component xilinx_simple_dual_port_1_clock_ram is 
    generic (
    RAM_WIDTH : integer, --< what is wrong here?
    RAM_DEPTH : integer,
    RAM_PERFORMANCE : string,
    INIT_FILE : string
    );
port 
    (
    addra : in std_logic_vector(clogb2(RAM_DEPTH)-1) downto 0);
    addrb : in std_logic_vector(clogb2(RAM_DEPTH)-1) downto 0); 
    dina  : in std_logic_vector(RAM_WIDTH-1 downto 0);
    clka  : in std_logic;
    wea   : in std_logic;
    enb   : in std_logic;
    rstb  : in std_logic;
    regceb: in std_logic;
    doutb : out std_logic_vector(RAM_WIDTH-1 downto 0)
    );

    end component;

begin
ramA: xilinx_simple_dual_port_1_clock_ram
     generic map (
     RAM_WIDTH => 18,
     RAM_DEPTH => 1024,
     RAM_PERFORMANCE => "HIGH_PERFORMANCE",
     INIT_FILE => "" 
    )
      port map  (
     addra  => addra, 
     addrb  => addrb, 
     dina   => dina,  
     clka   => clka,  
     wea    => wea,   
     enb    => enb,   
     rsta   => rsta,  
     regceb => regceb,
     doutb  => doutb 
    );

The other signals have been taken care of, including the port mapping to the bram module. I am getting a syntax error in the generic declaration.

Also there was an extra bracket on the addra and addrb, which I noticed later. — Vighnesh Velayudhan
– Vighnesh Velayudhan, Commented Jun 1, 2018 at 9:14
Provide a minimal reproducible example. You can't have an empty interface list for entity main, the separator for generic interface declarations should be a ';' , you have too many closing parens in addra and addrb (remove those after the 1s), you don't declare the actual signals for port map and you're missing a context clause (ieee; ieee.std_logic_1164.all;) There's no clog2b visible. You mislabeled actual rstb rsta in the ramA port map. Et Voila! - no syntax error. There is no requirement for a default value unless there is no actual provided for your generics. Provide the entire error message(s) as well. — user1155120
– user1155120, Commented Jun 1, 2018 at 13:02

Oldfart · Accepted Answer · 2018-06-01 09:09:25Z

1

You must give a generic a default value:

RAM_WIDTH : integer := 16;
--                       ^

Also use ; not ,

edited Jun 1, 2018 at 9:09

answered Jun 1, 2018 at 9:03

Oldfart

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4 Comments

Vighnesh Velayudhan Over a year ago

Yes I added that too, but it is still having a syntax error.

generic (  RAM_WIDTH : integer := 16,  RAM_DEPTH : integer := 1024,  RAM_PERFORMANCE : string := "LOW_LATENCY",  INIT_FILE : string := "" );

Matthew Over a year ago

You do not have to give a generic a default value. The problem is the comma.

user1155120 Over a year ago

IEEE Std 1076-2008 6.5.6.2 Generic clauses "The value of a generic constant may be specified by the corresponding actual in a generic association list. If no such actual is specified for a given formal generic constant (either because the formal generic is unassociated or because the actual is open), and if a default expression is specified for that generic, the value of this expression is the value of the generic. It is an error if no actual is specified for a given formal generic constant and no default expression is present in the corresponding interface element."

Topa Over a year ago

That clause only applies to entity not component because in a component the value is given by the generic association list (aka generic map)

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