Can't infer register error when output array type as port in vhdl

I'm new to VHDL. Currenty I'm trying to read a frame of multiple bytes via UART and output them as an array to decode later.

I'm using array type as the output port (or is there anything better, you guys can suggest it for me, please).

library ieee;
use ieee.std_logic_1164.all;

package pkg is
    type frame_type is array (natural range <>) of std_logic_vector(7 downto 0);
end package;

package body pkg is
end package body;

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg.all;

entity read_frame is
port(
    CLK         : in std_logic;
    dout_valid  : in std_logic;
    data_in         : in std_logic_vector(7 downto 0);
    data_out        : out std_logic_vector(19 downto 0);
    frame_out   : out frame_type(0 to 9);
    frame_check : out std_logic
);
end read_frame;

architecture arch of read_frame is
--type frame_type is array(0 to 9) of std_logic_vector(7 downto 0);
signal frame_duration: std_logic;
signal frame : frame_type(0 to 9);
signal count : natural range 0 to 9 := 9;
signal data  : std_logic_vector(7 downto 0);
--signal frame_t : frame_type;

begin
    process(CLK, dout_valid)
        begin
            if (rising_edge(dout_valid)) then
                if (rising_edge(CLK)) then
             --Getting data
                data <= data_in;
                if (data = "11111111") then  --Start frame
                    count <= 0;
                    frame_duration <= '1';
                    frame <= (others => (others => '0'));
                elsif (data = "00000000") then  -- end frame
                    count <= 0;
                    frame_duration <= '0';
                else
                    frame(count) <= data;
                    count <= count + 1;
                end if;
            end if;
        end if;
    end process;

    process(CLK, frame_duration)
        begin
            if (falling_edge(frame_duration)) then
                frame_out <= frame;
            end if;
        end process;
    frame_check <= frame_duration;
end arch;

However, I keep getting these errors

Error (10821): HDL error at read_frame.vhd(39): can't infer register for "frame[9][0]" because its behavior does not match any supported register model
Error (10821): HDL error at read_frame.vhd(39): can't infer register for "frame[9][1]" because its behavior does not match any supported register model

And so on. I thought the array I use is only 1 dimension? Maybe the way I assign the array is wrong. If not, how to you assign array member by index? Thank you in advance for taking your time to help me.