How I make an output logic signal a real output pin?

Question

I am trying to take this signal : signal Fx3_bridge : std_logic_vector (1 downto 0);

To this output port: Fx3_A : out std_logic;

I also want to discard the less significant bit of my logic vector.

Matthew · Accepted Answer · 2019-07-11 14:37:47Z

1

A std_logic_vector is an array. Your std_logic_vector

signal Fx3_bridge : std_logic_vector (1 downto 0);

has two elements - 1 and 0. You index arrays in VHDL using brackets, so the most significant bit (strictly speaking: the left hand element) is

Fx3_bridge(1)

So, you want something like:

Fx3_A <= Fx3_bridge(1);

answered Jul 11, 2019 at 14:37

Matthew

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4 Comments

user1155120 Over a year ago

IEEE Std 1076-2008 15.2 Character set. Those are left and right parentheses and not left and right square or curly brackets. An indexed name (8.4) uses parentheses.

Matthew Over a year ago

@user1155120 In British English, they're brackets.

user1155120 Over a year ago

Entomology shows parentheses are used as defined in the Cambridge dictionary, commonly used in IEEE and ISO/IEC standards.

B. Go Over a year ago

It's often a good practice to not hard code the bit number, when possible, and in this case to use Fx3_bridge(Fx3_bridge'high) to keep its highest bit, even if the size changes later...

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