Is there any way to latch data in combinational circuit when it differs from zero and keep it latched as long as clear signal is '0'. So I have no clock signal, no latch trigger. I tried this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tester is
Port ( inData : in std_logic_vector(3 downto 0);
inClear : in std_logic;
outStatus : out std_logic_vector(3 downto 0)
);
end tester;
architecture Behavioral of tester is
signal Data : std_logic_vector(3 downto 0);
signal NotZero : std_logic;
begin
with inData select
NotZero <= '0' when "0000",
'1' when others;
Data <= inData when (NotZero = '1') else Data;
outStatus <= Data;
end Behavioral;
But when inData goes back to zeros outStatus does the same.