How does system verilog treat if statements in always_ff blocks

Question

always_ff @(posedge sysclk) begin
case(state) begin
  SOME_STATE begin
    if(some logic to check) begin
       variable1 <= 1;
       variable2 <= variable_a > 0 ? 0 : 1;
       end
    else begin
       variable1 <= variable_b > 0 ? 0 : 1;
       variable2 <= 1;
       end
    variable3 <= {variable1, variable2}; 
    end //this case
  endcase
end //always_ff

All variables are of type logic and are appropriately sized.

Will system verilog correctly evaluate the statements controlling var1 and 2 before assigning them into var3 or does it treat if statements within an always_ff as non-blocking? There're more else if's that have been removed for clarity of the question.

Matthew · Accepted Answer · 2019-12-06 08:53:19Z

A non-blocking assignment within an always_ff block infers a flip-flop. An if statement is irrelevant. So, in your example code, variable1, variable2 and variable3 will all behave like flip-flops in simulation and hence will become flip-flops after synthesis.

If you would prefer variable1 and variable2 to be combinational logic then you must use blocking assignments:

always_ff @(posedge sysclk) begin
case(state) begin
  SOME_STATE begin
    if(some logic to check) begin
       variable1 = 1;                           // <-----
       variable2 = variable_a > 0 ? 0 : 1;      // <-----
       end
    else begin
       variable1 = variable_b > 0 ? 0 : 1;      // <-----
       variable2 = 1;                           // <-----
       end
    variable3 <= {variable1, variable2}; 
    end //this case
  endcase
end //always_ff

If you want this then I would recommend you declare variable1 and variable2 inside the begin-end block:

always_ff @(posedge sysclk) begin
<some type> variable1;                          // <-----
<some type> variable2;                          // <-----
case(state) begin
    ...
    variable3 <= {variable1, variable2}; 
    end //this case
  endcase
end //always_ff

That will prevent any other always block from being able to see these variables, which will prevent the potential simulation races that would occur if some other always block could see them.

score 0 · Accepted Answer · 2020-01-21 17:45:20Z

The IF statement will represent the Boolean logic that will drive the value to your flops.

I would rather split the combinational logic in an always_comb process and the sequential logic in the always_ff.

always_ff @(posedge sysclk) begin
   if (something)
    variable1 <= value; // Non Blocking assignment in always_ff block, variable 1 will be a Flip-Flop
end //always_ff


always_comb begin
   if (something)
    variable2 = value; // Non Blocking assignment in always_comb block, variable2 won't be a flop in this case, but just a combinatinal logic.
end //always_comb

Your IF statement will infer the same logic, in both the always_ff and always_comb block the inferred logic will act as an enable to load the value into variable1.

I hope it clarify what you are asking.

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