Is it possible to declare module inputs at compile time in verilog?

Question

For instance, I have the following generate block:

localparam N = 4
localparam P = 16
genvar i;
generate 
    for(i=0;i<P;i=i+1)
        begin: dmnGen
        localparam [N-1:0]r = func_r(i);   
        and dmn(OUT[i], S[3][r[3]], S[2][r[2]], S[1][r[1]], S[0][r[0]], EN);
    end
endgenerate

I would like to add S[x][r[x]] inputs to the and gate based on parameter N. Is it possible to programmatically add inputs at compile time?

no, it is not possible in verilog. But you can always create a script which will generate verilog for you. — Serge
– Serge, Commented Mar 16, 2021 at 2:13

Greg · Accepted Answer · 2021-03-16 17:58:35Z

1

You cannot change the number of port connections based on a parameter. But you can either generate a set of cascading and gates, you better yet, use a reduction & operator.

localparam N = 4
localparam P = 16

genvar i,j;
  for(i=0;i<P;i=i+1) begin: dmnGen
    localparam [N-1:0]r = func_r(i);
    wire [N-1:0] p;
    assign OUT[i] = &p;
    for(j=0;j<N;j=j+1)
     assign p[j] = S[j][r[j]];
  end
endgenerate

edited Mar 16, 2021 at 17:58

Greg

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answered Mar 16, 2021 at 2:24

dave_59

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