Yosys synthesys - is this opimum?

Question

I'm using yosys to synthesize simple circuits and show how the result varies with the cell library. However, it looks like the result is not well optimized. I'm using the library vsclib013.lib downloaded from: http://www.vlsitechnology.org/synopsys/vsclib013.lib

E.g. I synthesize an adder composed by 4 full adders. Since I do not use Carry_in and Carry_out I do expect that an half adder is synthesized (XOR with two inputs) for the LSB adder. The result of the synthesis is the following.

Number of cells                 12
 cgi2v0x05                       4
 iv1v0x05                        4
 xor3v1x05                       4

It uses 4 cells that are XOR with three inputs. This is also clear from the graph of the circuit: graph obtained using the yosys command 'show'
The circuit is simply composed by four identical full adders and there is no optimization for the Carry_in being equal to '0' and for the Carry_out not being connected.

The script I used to syntesize is:

ghdl TOP_ENTITY
hierarchy -check -top TOP_ENTITY
proc; opt; memory; opt; fsm; opt
techmap; opt
read_liberty -lib vsclib013.lib
dfflibmap -liberty vsclib013.lib
abc -liberty vsclib013.lib -D 1000 -constr constraint_file_vsclib013.txt
splitnets -ports; opt
clean
write_verilog TOP_ENTITY.v
flatten
show -stretch -format pdf -lib TOP_ENTITY.v

Thank you for any suggestion to improve the synthesys.

Per Yosys documentation -full is an alias for -fine, so this seems redundant. Perhaps you could try with other options to opt such as -share_all and -purge, the first attempts a merge to cells that are driven from identical signals, this option is forwarded to opt_merge. The -purge option clears named left over or unconnected nets, again this option is passed implicitly to opt_clean. Additionally, you can add opt_demorgan to reduce the gate count. — kalgoritmi
– kalgoritmi, Commented Apr 13, 2021 at 14:15

etnapoli · Accepted Answer · 2021-04-15 15:17:36Z

3

Thx for your answer.

After some tries and errors I obtained good resutls by simply using flatten. I also added -full to the opt commands for (hopefully) good meaure. Now, my working script is like this:

ghdl TOP_ENTITY
hierarchy -check -top TOP_ENTITY
flatten
proc; opt -full; memory; opt -full; fsm; opt -full 
techmap; opt -full
read_liberty -lib vsclib013.lib
dfflibmap -liberty vsclib013.lib
abc -liberty vsclib013.lib -D 1000 -constr constraint_file_vsclib013.txt
splitnets -ports; opt -full
clean -purge
write_verilog TOP_ENTITY.v
flatten
show -stretch -format pdf -lib TOP_ENTITY.v

I also added -purge option to the clean command to get a nicer printed schematic.

edited Apr 15, 2021 at 15:17

answered Apr 15, 2021 at 15:00

etnapoli

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