Error by VCS tool on uvm_hdl_deposit usage on edaplayground

Question

I am trying to execute code @ https://www.edaplayground.com/x/e2Pe. The code seems to be error free. However, when trying to simulate with VCS tool, it is giving me below error:

UVM_ERROR: set: unable to write to hdl path (top.dut_inst.BOOT_MODE)
You may not have sufficient PLI/ACC capabilites enabled for that path
              10    3.1 Force failed...

It looks like I need to set some options, but I am not aware. I tried giving +vpi +acc, but that did not work out.

Here is the complete command:

vcs -licqueue '+vpi' '+pli' '+acc' '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc -CFLAGS -DVCS design.sv testbench.sv  && ./simv +vcs+lic+wait

Here is the relevant testbench code:

  if(uvm_hdl_deposit("top.dut_inst.BOOT_MODE",4'b0000)) begin
    $display($time,"\t1 Forced value...");
  end  else begin
    $display($time,"\t3.1 Force failed...");
  end

toolic · Accepted Answer · 2021-09-23 17:48:12Z

1

This warning message tells you what's wrong:

Warning-[DEPRECATED_OPTION] Deprecated option used
  The specified option '+acc' is deprecated.
  Please use '-debug_access+r+w+nomemcbk -debug_region+cell' instead.

When I replace +acc with -debug_access+r+w+nomemcbk -debug_region+cell, I no longer get UVM_ERROR messages, and I see this output:

              10    1 Forced value...
              20    1 Forced value...
              30    1 Forced value...

Here is the modified edaplayground

answered Sep 23, 2021 at 17:48

toolic

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ShaHbaZ AhMad · Accepted Answer · 2023-04-04 08:18:22Z

0

Simply adding -debug_all flag in command will solve your problem.

In my case, only -debug_all works. But in your case, -debug_access+all works fine. Here is the EDA link.

edited Apr 4, 2023 at 8:18

answered Mar 30, 2023 at 4:40

ShaHbaZ AhMad

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