Syntax error: invalid module item when declaring variables

Question

module fourbitadder(a,b,carry,s,outcar);
input [3,0]a,b;
input carry;
output  [3,0]s;
output outcar;     
wire c_1,c_2,c_3,c_4;
wire [3,0]p;                                    //error is here
fulladder fa1(a[0],b[0],carry,p[0],c_1);
fulladder fa2(a[1],b[1],c_1,p[1],c_2);          //error is here
fulladder fa3(a[2],b[2],c_2,p[2],c_3);
fulladder fa4(a[3],b[3],c_3,p[3],c_4);
assign s=p;
assign outcar = c_4;
endmodule

syntax error
 error: invalid module item.
syntax error
 error: invalid module item.

ToTamire · Accepted Answer · 2021-11-14 09:34:28Z

1

Width of wire or register is declared as [MSB:LSB] not [MSB,LSB].

module fourbitadder (
        a,
        b,
        carry,
        s,
        outcar
);

    input [3:0] a, b;
    input carry;
    output [3:0] s;
    output outcar;

    wire c_1, c_2, c_3, c_4;
    wire [3:0] p;

    fulladder fa1(a[0],b[0],carry,p[0],c_1);
    fulladder fa2(a[1],b[1],c_1,p[1],c_2);
    fulladder fa3(a[2],b[2],c_2,p[2],c_3);
    fulladder fa4(a[3],b[3],c_3,p[3],c_4);

    assign s = p;
    assign outcar = c_4;

endmodule

answered Nov 14, 2021 at 9:34

ToTamire

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Comments

toolic · Accepted Answer · 2021-11-14 12:21:15Z

It looks like you are using iverilog as a simulator. Sometimes you can get more helpful error messages with other simulators. This is the case if you compile your code on edaplayground when you sign up for a free account. For example, using the Cadence simulator, we get:

input [3,0]a,b;
        |
xmvlog: *E,SVEXTK (testbench.sv,2|8): expecting a ':' or ']' (following the first expression in a packed/unpacked dimension).

output  [3,0]s;
          |
xmvlog: *E,SVEXTK (testbench.sv,4|10): expecting a ':' or ']' (following the first expression in a packed/unpacked dimension).

wire [3,0]p;                                    //error is here
       |
xmvlog: *E,SVEXTK (testbench.sv,7|7): expecting a ':' or ']' (following the first expression in a packed/unpacked dimension).

It's so much better when you let the tools tell you exactly what the problem is: replace the comma with a semicolon in all the vector ranges.

  input [3:0]a,b;
  input carry;
  output  [3:0]s;
  output outcar;     
  wire c_1,c_2,c_3,c_4;
  wire [3:0]p;

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