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I have a board that has an NXP iMX8M-Plus processor and an Intel Arria 10 GX FPGA on it. I want to configure the FPGA using the iMX8M-Plus processor through passive serial interface of the FPGA. I use custom yocto based image which has Linux Kernel v5.4 for the system and I have noticed that this kernel has special drivers for the operation that I needed and the driver is in ./drivers/fpga/altera-ps-spi.c file.

I added following line to Linux Kernel defconfig before compiling to include the driver:

CONFIG_FPGA_MGR_ALTERA_PS_SPI=y

And changed Device Tree file as explained here ./Documentation/devicetree/bindings/fpga/altera-passive-serial.txt in the Kernel source code by adding following lines:

/ {
    ...
    ...
    altera_region {
        compatible = "fpga-region";
        fpga-mgr = <&altera_spi>;
        firmware-name = "test.rbf";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
    };
};

/* Verdin SPI_1 */
&ecspi1 {
    status = "okay";

    altera_spi: altera-spi@0 {
        compatible = "altr,fpga-arria10-passive-serial";
        spi-max-frequency = <80000000>;
        reg = <0>;
        nconfig-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
        nstat-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>;
        confd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;          
    };        
};

So far it is ok, the linux boots properly and I have following folder under /sys/class/fpga_manager folder.

root@localhost:/sys/class/fpga_manager/fpga0# ll
total 0
-r--r--r-- 1 root root 4096 Sep 23 12:38 consumers
lrwxrwxrwx 1 root root    0 Sep 23 12:38 device -> ../../../spi1.0
-r--r--r-- 1 root root 4096 Sep 23 12:38 name
lrwxrwxrwx 1 root root    0 Sep 23 12:38 of_node -> ../../../../../../../../../../firmware/devicetree/base/soc@0/bus@30800000/spi@30820000/altera_spi@0
drwxr-xr-x 2 root root    0 Sep 20 10:45 power
-r--r--r-- 1 root root 4096 Sep 23 12:38 state
-r--r--r-- 1 root root 4096 Sep 23 12:38 status
lrwxrwxrwx 1 root root    0 Sep 20 10:44 subsystem -> ../../../../../../../../../../class/fpga_manager
-r--r--r-- 1 root root 4096 Sep 23 12:38 suppliers
-rw-r--r-- 1 root root 4096 Sep 20 10:44 uevent

My problem starts here. Basically I couldn't find any documentation or an example about how to use this driver. I have an rbf file generated by Quartus and simply I should be able to send this file to the FPGA over this driver. Do you have any idea about what should be the next step that I need to follow?

Thank you.

Improve this question
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  • The usual way is to define a compatible = "fpga-region"; node in the device tree (see the bindings). That could be fully populated in the original device tree, or left mostly empty to be filled in by a device tree overlay. But the mostly empty version should at least have a fpga-mgr property set to the phandle of your FPGA manager node: fpga-mgr = <&altera_spi>; and have #address-cells, #size-cells and maybe ranges properties. Commented Feb 9, 2022 at 15:11
  • @IanAbbott Thank you for the comment. I updated the device-tree accordingly, you can see it in the question updated. But FPGA is still unprogrammed. Commented Mar 23, 2022 at 10:40
  • 1
    Another option is for some external module to interact with the FPGA bridges and FPGA manager directly, bypassing the FPGA region stuff. E.g. of_fpga_mgr_get() or fpga_mgr_get() to get a reference to the FPGA manager, of_fpga_bridge_get_to_list() or fpga_bridge_get_to_list() to get references to the bridges, fpga_mgr_lock() to lock the manager, fpga_bridges_disable() to disable the bridges, fpga_mgr_firmware_load() or fpga_mgr_load() to load the firmware, [continued in next comment] Commented Mar 23, 2022 at 17:48
  • 1
    [continued from previous comment] fpga_bridges_enable() to re-enable the bridges, fpga_mgr_unlock() to unlock the FPGA manager, fpga_bridges_put() to put references to the bridges, fpga_mgr_put() to put reference to FPGA manager. Commented Mar 23, 2022 at 17:50
  • 1
    BTW the kernel patches I mentioned for loading DT-Overlays from userspace (via configfs) can be found at topic/overlays. Commented Mar 23, 2022 at 18:03
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