I am doing a university project in which i have to build a I2C which have only one slave and will have to transmit a data with 5 bits, 4 bits for the number which is in the range of 0 to 9 and 1 bit to read or write, i'm using a DE10-LITE with VHDL for this project, which has a 50 Mhz default clock, i was looking into the "ALTPLL" inside quartus prime but i can't find the option to set my clock to 100kbps, i did find in the in some forums that the "Set up PLL in LVDS mode" enables that, but for some reason quartus won't let me activate it. My SDA will be 100kbps, and the SCL 50mhz.
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The FPGA code is 10M50DAF484C7GLucca Machado– Lucca Machado2022-07-09 20:51:31 +00:00Commented Jul 9, 2022 at 20:51
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1See the I2C Specification. The clock is not continuous and can be the output of a state machine.user16145658– user161456582022-07-10 07:33:09 +00:00Commented Jul 10, 2022 at 7:33
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This clock is very slow, so you don't need to use a PLL to generate it. If your FPGA clock is a multiple of 100 kHz, then you can easily generate the I2C clock with simple clock-divider logic.Harry– Harry2022-07-10 20:25:47 +00:00Commented Jul 10, 2022 at 20:25
2 Answers
As the Other people have said: You don't need a PLL for that. If you already have a default clock of 50MHz then you just need to divide that by 500, using a counter, and then you have your 100kHz clock.
Anyways, you would want to start the counter only when there is a request on the bus. So user16145658 is correct: The generated clock should be the output of your state machine.
Comments
You don't need to change the clock of the FPGA, since you are using an FPGA, you only need to implement an i2c core to communicate with the i2c device.
And the i2c specification specifies the rate of i2c
Standard mode (Sm) 100 kbit/s
Fast mode (Fm) 400 kbit/s