Hello I am trying to learn VHDL in xilinx ISE enviroment and I can not get this code to work and i do not know why. I have tried single quotes using/not using ands, but nothing works. Could someone please help me?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity teh_3 is
Port ( thermo_input : in STD_LOGIC_VECTOR(3 DOWNTO 0);
too_hot : out STD_LOGIC;
too_cold : out STD_LOGIC;
just_right : out STD_LOGIC);
end teh_3;
architecture Behavioral of teh_3 is
begin
IF thermo_input < "1000" THEN
too_cold <='1' and
too_hot <='0' and
just_right <='0';
ELSIF thermo_input > "1011" THEN
too_hot <='1' and
too_cold <='0' and
just_right <='0';
ELSIF thermo_input > "0111" THEN
just_right <='1' and
too_hot <='0' and
too_cold <='0';
ELSE
just_right <='0' and
too_hot <='0' and
too_cold <='0';
END IF;
end Behavioral;
ERROR:HDLParsers:164 - "/home/student/kokeilu/kokeil.vhd" Line 40. parse error, unexpected IF
Thanks!