What will this synthesize to in DC?

Question

What will the be DC synthesis output? I don't have access to DC. If a=1 and b=1 will both address locations get updated ? Addr1 and addr2 are logic as well and guaranteed not to be equal.

logic [3:0][31:0] cache;

always_ff .... begin
.....reset...

if (a) 
  cache[addr1] <= data1;


if (b)
  cache[addr2] <= data2;

end

There are free synthesis tools out there, e.g. XST, Vivado synthesis, whatever Intel's FPGAs use, Lattice's tool, etc — nanofarad
– nanofarad, Commented Oct 12, 2022 at 15:32
This is going to depend on the declaration of cache and the target technology you are mapping to. If cache is an array of bits, or can fit into a register file instead of a memory, then no problem. — dave_59
– dave_59, Commented Oct 13, 2022 at 0:46

dave_59 · Accepted Answer · 2022-10-13 19:22:22Z

0

Yes, this will synthesize into a 128-bit register with each input bit fed by a 3-to-1 multiplexor selection a bit from data1, data2, or the previous output bit of the register. The selection logic will be a combinational expression of the addresses, a, and b.

answered Oct 13, 2022 at 19:22

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

What will this synthesize to in DC?

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related