I am trying to describe a RS asynchronous latch in VHDL. I receive this error from vivado.
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets S_IBUF] >
S_IBUF_inst (IBUF.O) is locked to IOB_X0Y93 and S_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7
The code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RSlatch is
Port (
R, S : in std_logic;
Q: out std_logic
);
end RSlatch;
architecture Behavioral of RSlatch is
begin
process (R, S)
variable aux : std_logic := '0';
begin
if (R = '1') then
aux := '0';
elsif(S = '1') then
aux := '1';
else
aux := aux;
q <= aux;
end if;
end process;
end Behavioral;
I am not using a clock so I do not understand why do I receive this error.