In post-synthesis simulation on Vivado, the netlist flattens a 2D array to a 1D array. How can we adapt the testbench to the change of these ports? For example in DUT instantiation, feeding values to this port through $fscanf function.
Example:
reg signed [13-1:0] mac_ofdIsymbol_tqs [1:0];
This port is now flattened in the netlist to mac_ofdIsymbol_tqs[0][12:0] and mac_ofdIsymbol_tqs[1][12:0]
I tried searching online for the error, but trials stated there were in vain.
How can we adapt the testbench to the change of these ports?
A common approach is to use the `ifdef compiler directive to make different port connections to your DUT instance in the testbench. Here is a pseudocode example:
`ifdef GATES
.mac_ofdIsymbol_tqs[0] ( mac_ofdIsymbol_tqs[0] ),
.mac_ofdIsymbol_tqs[1] ( mac_ofdIsymbol_tqs[1] ),
`else
.mac_ofdIsymbol_tqs ( mac_ofdIsymbol_tqs ),
`endif
The post-synthesis simulation is run using a macro named GATES. Many simulators allow you to pass an argument to the simulation command such as +define+GATES.
Refer to IEEE Std 1800-2017, section 22.6:
`ifdef, `else, `elsif, `endif , `ifndef
Also refer to your Vivado documentation on running simulation with different compiler options.