I am having a frustrating time designing a linear feedback shift register where there is a need to use Altera's LPM's, in this case the LPM_SHIFTREG. This must be used as I have an assignment and exam on these components within days of writing this and of course have put this on the backburner for a while, so I appreciate if I could get some help to initialise and correctly configure the code.
The main code is instantiated within a top level component among other things, which are working correctly, so I have included the least amount of code needed to test this as a MWE. Right now I have no way of telling if any bits are shifted as the output is all zeros - obviously a LFSR would just feedback all zeros, so maybe without an initial state of some 1's and 0's it could be shifting zeros. So through my own work I have tried to use an initialise state, such that the lfsr_out will have some bits XOR as feedback to the lfsr_in. I have tried adding a reset state that should initialise for some time and then let the output of the LFSR take over and away it should go. This was not the case, so the following error occurs with the initialisation process:
Yes, I understand I cannot drive many inputs at the same time so how can I overcome this? I have tried looking at VHDL LFSR's but with the use of the LPMs, which there are hardly any examples of such. Ideally, I would need to keep the LPM_SHIFTREG as this component is on an exam question, so I would like some peace of mind that I will not write complete rubbish! Here is a screenshot of the ModelSim signals for the current code where the initialisation process is removed:
LFSR_comp.vhd
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library altera_mf;
library lpm;
use lpm.lpm_components.ALL;
entity LFSR_comp is
PORT (
clk : in std_logic;
pa_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(9 downto 0)
);
end LFSR_comp;
architecture LFSR_comp_bhv of LFSR_comp is
signal lfsr_in : std_logic := '0';
signal lfsr_out : std_logic_vector(9 downto 0);
signal lfsr_clock : std_logic := '0';
signal lfsr_rst : std_logic := '1';
signal initial_state : std_logic_vector(9 downto 0) := "1010110111";
begin
-- Toggle the lfsr_clock using PA as a clk divider
lfsr_clock <= pa_in(7);
-- Initialization process
-- process(lfsr_in, lfsr_rst, lfsr_out, initial_state)
-- begin
-- if lfsr_rst = '1' then
-- lfsr_out <= initial_state;
-- lfsr_rst <= '0';
-- end if;
-- end process;
-- Load the initial state into the shift register
lfsr : LPM_SHIFTREG
generic map (
LPM_WIDTH => 10,
LPM_DIRECTION => "LEFT"
)
port map (
data => lfsr_out,
clock => lfsr_clock,
q => lfsr_out,
shiftin => lfsr_in
);
lfsr_in <= lfsr_out(7) xor lfsr_out(3) xor lfsr_out(2) xor lfsr_out(0);
data_out <= lfsr_out;
end LFSR_comp_bhv;
LFSR_top.vhd
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.ALL;
entity LFSR_top is
PORT (
clk : in std_logic;
fsw_in : in std_logic_vector(7 downto 0);
pa_probe_out : out std_logic_vector(7 downto 0);
data_out : out std_logic_vector(9 downto 0)
);
end LFSR_top;
architecture LFSR_top_bhv of LFSR_top is
component PA_comp
PORT (
CLK : IN STD_LOGIC := '1';
FSW : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
DATA_OUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;
component LFSR_comp
PORT (
CLK : in std_logic;
PA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(9 downto 0)
);
end component;
signal pa_data_out : std_logic_vector(7 downto 0) := (others => '0');
signal ask_data_out : std_logic_vector(9 downto 0) := (others => '0');
begin
-- Phase Accumulator
phase_acc : PA_comp
PORT MAP (
CLK => clk,
FSW => fsw_in,
DATA_OUT => pa_data_out
);
-- LFSR
lfsr : LFSR_comp
PORT MAP (
CLK => clk,
PA_IN => pa_data_out,
DATA_OUT => ask_data_out
);
data_out <= ask_data_out;
end LFSR_top_bhv;
PA_comp.vhd
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library altera_mf;
library lpm;
use lpm.lpm_components.ALL;
entity PA_comp is
PORT (
clk : in std_logic;
fsw : in std_logic_vector(7 downto 0); -- Assuming an 8-bit FTW
data_out : out std_logic_vector(7 downto 0)
);
end PA_comp;
architecture PA_comp_bhv of PA_comp is
signal add_out : std_logic_vector(7 downto 0) := (others => '0');
signal q_out : std_logic_vector(7 downto 0) := (others => '0');
begin
-- LPM_ADD_SUB for phase accumulator
addnsub : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 8,
LPM_DIRECTION => "ADD"
)
PORT MAP (
DATAA => fsw,
DATAB => q_out,
RESULT => add_out
);
-- LPM_FF for phase accumulator
dff : lpm_ff
GENERIC MAP (
LPM_WIDTH => 8,
LPM_FFTYPE => "DFF"
)
PORT MAP (
DATA => add_out,
CLOCK => clk,
Q => q_out
);
data_out <= q_out;
end PA_comp_bhv;
LFSR_tb.vhd
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.ALL;
entity LFSR_tb is
end LFSR_tb;
architecture LFSR_tb_bhv of LFSR_tb is
signal clk : std_logic := '0';
signal fsw_in : std_logic_vector(7 downto 0) := (others => '0');
signal pa_probe_out : std_logic_vector(7 downto 0) := (others => '0');
signal data_out : std_logic_vector(9 downto 0) := (others => '0');
constant clk_period : time := 10 ns;
begin
uut: entity work.LFSR_top
port map (
clk => clk,
fsw_in => fsw_in,
pa_probe_out => pa_probe_out,
data_out => data_out
);
-- Clock process def.
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stimulus_process: process
begin
fsw_in <= "00000001";
wait for 2560 ns;
end process;
end LFSR_tb_bhv;
