Modelsim error flag in integer wrapping around - change to vhdl code not possible

Question

I have an old VHDL code which I need to run a simulation for with Modelsim. This code "includes" a warp around condition which is of no consequence in real hardware but fails in simulation. I know this should not be written like this as the implementation depends on the synthesis tool, but it was written 20 years ago and I have to deal with it now.... Within a state machine the next state is determined by the value of a signal decreased from a preloaded value downto 0. Unfortunately the decrement line is not within the If then else statement, thus "bitcounter" is decreased also when being zero. The wrapped around value is not used for anything within the code (in one of the "later" states, the signal is preloaded again), thus everything is fine in hardware.

signal definition: Bitcounter : integer range 0 to 11;

problematic code snippet

process(clk) begin if rising_edge(clk) then

case state is when ....

...

when GET_DATA_2 => IF (Bitcounter = 0)
THEN STATE <= LAST_CYCLES_HIGH;
ELSE STATE <= GET_DATA1; END IF; Bitcounter <= Bitcounter-1; ...

Modelsim fails as bitcounter is decremented to -1

Is there any option to compensate this bad code by a simulation command, either by declaring "-1" to be "allowed" (extending the range "on Modelsim side") or supressing this particular error in simulation?

While the easiest way is to change the VHDL code for sure, this will finally end in different configuration data which should be avoided...

perhaps try this switch found in the VCOM documentation: -nocheck Disables run time range checking. In some designs, this results in a 2X speed increase. Range checking can be enabled using -rangecheck. — Matthias Schweikart
– Matthias Schweikart, Commented Apr 3, 2024 at 8:34
Hi, I tried this w/o effects... as the problem is not with the compilation. I tried similiar with the VSIM command using the -warning option. (vsim -warning 3421, but this severity of this error ((vsim-3421) Value -1 is out of range 0 to 11.) cannot be changed (what makes sense from simulation point of view) — Carlhermann Schlehaus
– Carlhermann Schlehaus, Commented Apr 3, 2024 at 10:10

EML · Accepted Answer · 2024-04-03 11:08:22Z

0

Has this code ever run? If so, it was presumably run without range checking, as the comment suggests.

Note that Modelsim doesn't 'fail'; you just get an assertion error to show that the value is now out of range. That's how ranges work: there's no implied modulo arithmetic; it's just a check. If you don't like this, take out the subtype declaration (range) and just use a plain integer. However, the original designer presumably used the range for a reason, so it would probably be better to fix the decrementing operation so that it first checks if the value is zero, and then wraps to 11 (or Bitcounter'high).

Note that, if Bitcounter is actually synthesised, you should leave the range in and just fix the decrement.

EDIT

Ok, so following your comment, the code was not previously simulated, but you must now simulate it, so you must change the code, but you must ensure that you don't get "different configuration data"?

1: you're presumably on an FPGA (because you say 'configuration data', and the simulation doesn't work, which is a give-away). The configuration data will change whatever you do, since it contains metadata (for Xilinx bitfiles, anyway). However, the MCS file (if you generate one) will remain the same if your changes don't affect the implementation

2: Don't change the range. range 0 to 11 will be synthesised as 4 bits; if you change it, it might be different. The tool might optimise it back to 4 bits, but this won't guarantee an identical MCS file

3: You can reduce the severity of this (programming, not ModelSim) error in simulation, but that's not a good idea; you might miss 'real' errors

4: the translate pragmas are your friend. Wrap your fix (ie. check the value before decrementing) in a code block like this:

 -- synthesis translate_off
 your simulation-only fix here
 -- synthesis translate on

edited Apr 3, 2024 at 11:08

answered Apr 3, 2024 at 9:28

EML

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2 Comments

Carlhermann Schlehaus Over a year ago

Hi, the code runs fine in real hardware, as the uncertaintiy of "whats happening with "bitcounter" on decrementing below 0 has no effect on the behaviour. The code never ran in simulation - thus the decrement into the "else" choice was implemented in the code. This results in a well running simulation but a mismatch between simulated and synthesized code. Therefore the idea was to either supress the error (which seems to be not foreseen by modelsim, as this can cause fatalities) or use apply a modification of the range for the "simulation representation" of the interger...

Carlhermann Schlehaus Over a year ago

Hi, as the old toolchain (max+plusII) does not automatically support translate pragmas and at the end of the day ModelSim functional simulation uses ModelSim compiler anyway (being different to max+plusII) I think I'll have to use two baselines (one for funct. sim with the fixes to prevent out of range error during sim and the original code for synthesis and gate level sim). For being curious - how could the message severity be reduced - trying this I got a "response" form ModelSim that change is not possible for this error)... Thanks a lot :-)

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