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I'm a newbie in VHDL Programming and I am having trouble with this VHDL code (sync counter). The variable Q_AUX_4 is never assigned to the output Q_OUT because when I try to run simulation, using modelsim, is always set to "UUUU". This is even more strange because Q_AUX_4 is initialized to "0000", so It's like that line is never triggered. Thank you for every response

counter4.vhdl
LIBRARY IEEE;
USE ieee.STD_LOGIC_1164.all;

ENTITY COUNTER4 IS
    PORT ( EN,CK,CL: IN STD_LOGIC;
           Q_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           T_OUT_4: OUT STD_LOGIC);
END COUNTER4;

ARCHITECTURE BEHAVIOR OF COUNTER4 IS

COMPONENT T_FLIP_FLOP IS
    PORT ( T,CLK,CL: IN STD_LOGIC;
        Q, T_OUT: OUT STD_LOGIC);
END COMPONENT;

SIGNAL Q_AUX_4 : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS=>'0');
SIGNAL T_AUX: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

F0: T_FLIP_FLOP PORT MAP(EN,CK,CL,Q_AUX_4(0),T_AUX(0));
F1: T_FLIP_FLOP PORT MAP(T_AUX(0),CK,CL,Q_AUX_4(1), T_AUX(1));
F2: T_FLIP_FLOP PORT MAP(T_AUX(1),CK,CL,Q_AUX_4(2), T_AUX(2));
F3: T_FLIP_FLOP PORT MAP(T_AUX(2),CK,CL,Q_AUX_4(3), T_AUX(3));
Q_OUT <= Q_AUX_4;
T_OUT_4 <= (T_AUX(2) AND Q_AUX_4(3));


END BEHAVIOR;

T_flip_flop.vhdl

LIBRARY IEEE;

USE ieee.std_logic_1164.all;

ENTITY T_flip_flop is
PORT ( T,CLK, CL: IN STD_LOGIC;
    Q, T_OUT: OUT STD_LOGIC);
end T_flip_flop;

Architecture Behavior of T_flip_flop is

SIGNAL Q_AUX: STD_LOGIC := '0';


BEGIN
PROCESS (T,CLK,CL) 
  BEGIN 
  if ((CLK = '1' AND CLK'EVENT) AND T = '1') THEN
    Q_AUX <= NOT Q_AUX;
   else Q_AUX <= Q_AUX;
   END IF;

   IF (CL = '1') THEN Q_AUX <= '0';
   END IF;
   Q <= Q_AUX;
   T_OUT <= (Q_AUX AND T);

END PROCESS;
END behavior;

I tried to put the assignment in a process triggered by Q_AUX_4 but the result is the same. I expect Q_OUT to be a copy of Q_AUX_4

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  • Provide a minimal reproducible example to replicate the problem and demonstrate any solution. Here a testbench and and indication at what simulation time you expected a different value on Q and why. Questions and their answers are intended for future readers with similar issues led to your question by search. Note as yet the answer doesn't yet explain why the less than specific problem occurred nor how the answer corrected it. Matthias is right about synthesis eligible syntax without citing or providing a link to an authoritative reference. A clearly stated problem can be used to searh for duplicates here. Commented Apr 8, 2024 at 21:00

1 Answer 1

Reset to default
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I added a testbench and in my simulation of your original code with GHDL q_out is counting and is always different from "UUUU". So there might be a problem with your testbench which you did not show. In my testbench the rising clock edge of ck is at 10ns, 20ns, ... I stimulated cl and en in this way:

cl <= '0'; -- for all time
en <= '0', '1' after 21 ns;

Some hints to your design:

In t_flip_flop the input cl is behaves as an asynchronous reset.

In t_flip_flop the input t behaves like an synchronous enable.

To be sure that synthesis tools understand for sure what you want, most of the times a clocked process with asynchronous reset and synchron enable is described in this way:

process(clk, cl)
begin
    if cl='1' then
        q_aux <= '0';
    elsif clk='1' and clk'event then
        if t='1' then
            q_aux <= not q_aux;
        end if;
    end if;
end process;

Be aware that I modified the sensitivity list in the code above: The signal t should not be part of the sensitivity list, as t is only relevant when there is a rising clock edge.

Be aware that I moved in the code above

q <= q_aux;
t_out <= q_aux and t;

out of the process, because in your implementation the signal q changes its value always at the falling clock edge because:

As the assignment to q_aux is done after the clocked process finishs, and q_aux is not part of the sensitivity list (which is correct for a clocked process), the assignment "q <= q_aux" takes place changes the value at q when the process is triggered the next time, which is the falling clock edge.

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3 Comments

... the assignment "q <= q_aux" takes place when the process is triggered the next time, which is the falling clock edge. No. VHDL is event driven. A concurrent signal assignment statement represents an equivalent process with a sensitivity list containing all evaluated signals, here q_aux. The assignment to q occurs on an event on q_aux a simulation cycle after the rising edge of clk. All pending processes resume and subsequently suspend in wait statements (here implicit) before any projected output waveform queued signals are updated in the following simulation cycle.
A process statement with a sensitivity list has an implicit wait statement as it's last statement with it's time out sensitivity clause containing the process statement's sensitivity clause elements. The original code could have q_aux added to the sensitivity list, retaining T, for simulation although that would not address Intel's nebulous synthesis eligibility requirements. You don't demonstrate the non-specific problem.
As @user16145658 stated correctly, "takes place" is wrong and was therefore substituted by "changes the value at q".

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