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I'm working with STM32h745 SPI to interface adc ADS7046. I trying to achieve sampling rate at least 2msps.

Below I attach some snap for SCLK and CS signal. i trying to minimize time between sclk regenerate pulses. it is taking long time so I can't be able to reach sampling rate. I trying with different methods like Interrupt, DMA but same got. so can you suggest possible method to acquiring max 2msps sampling rate using stm32h745.

Red= CS signal, Blue= SCLK.... controller SYS clock frequency 400Mhz

Tcycle SCLK sys clock configuration SCLK regenerate spi code

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  • Welcome to Stack Overflow. First thing please don't post images of your code. You can inline smaller images. Looks like you are an order of magnitude short of where you want to be. Looking at the waveform I doubt if you can get more than ~4-5x faster. Your best bet is a device driver with a decent sized FIFO buffer on it . I doubt if user level code can hack it. Commented May 14, 2024 at 8:52
  • HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; uint32_t temp_sr_reg; uint16_t init_max_data_in_fifo; init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); #if defined (GNUC) IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif / __GNUC / / Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); Commented May 14, 2024 at 9:24
  • i used spi with polling method. Commented May 14, 2024 at 9:28
  • Please, show your SPI configuration. Clock config looks OK. Please, show all code as text, not as screenshots. Commented May 14, 2024 at 12:24
  • Hello @llya, I'm not able to attch file here. i just configure spi in receive only master mode and trying to read external adc with spi polling method. i working fine but sampling rate not getting as my requirement. bcoz for sclk generate 16pulses then then it taking time again 16pulse generate for next cycle and so on. my problem is that how can i minimize sclk regeneration time here.. means any possibility to changes in HAL driver code and where. Commented May 14, 2024 at 12:38
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