1

Here's my code:

//`timescale 1ns / 1ps

module FourBitLedToggle(
    input res,
    input Clk,
     output [3:0] led
     
    );
    
reg [27:0] count;//for 1 second check
reg clk1s;//1 second clock
reg [3:0]counterled;

always @(posedge Clk)
begin

if(res==1'b1)  //CHECK RESET
begin
clk1s<=1'b1;
count<=0;
end

else begin

if(count==28'h2FAF080)//0.5 sec //CHECKS IF SEC COMPLETED
begin

clk1s <= ~clk1s;

count <= 0;
end
else begin
 count <=count+1;
end
end
end

always @(posedge clk1s)  //CHECKS EVERY POSITIVE EDGE OF CLK1S
begin
counterled<=counterled+4'b0001;
end

assign led=counterled;

endmodule

Here's the testbench im using: //I only need clk i guess

`timescale 1us / 1us

module FourBitToggleCheck;

    // Inputs
    reg res;
    reg Clk;

    // Outputs
    wire [3:0] led;

    // Instantiate the Unit Under Test (UUT)
    FourBitLedToggle uut (
        .res(res), 
        .Clk(Clk), 
        .led(led)
    );

    initial begin
        // Initialize Inputs
        res = 0;
        Clk = 0;

        
        forever 
          #10 Clk=~Clk;

    end
      initial begin
       res=1;
       #20;
       res=0;
     end
endmodule

Here's the result in my simulation:

enter image description here

I am not able to understand how to bring the required incremental behaviour of the 4-bit counter in the simulation. Any help shall be appreciated.

0

1 Answer 1

1

28'h2FAF080 is the same as 28'd50_000_000. This is too much by a factor of 2000. It should be 25_000. Change:

       if(count==28'h2FAF080)//0.5 sec //CHECKS IF SEC COMPLETED

to:

       if(count==28'd24_999)//0.5 sec //CHECKS IF SEC COMPLETED

Now, clk1s has a period of 1s.

Then you need to reset counterled to 0 to eliminate the unknown (x) on the output:

   always @(posedge clk1s)  //CHECKS EVERY POSITIVE EDGE OF CLK1S
     begin
        if (res) begin
            counterled <= 0;
        end else begin
            counterled <= counterled + 4'b0001;
        end
     end
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