I have seen some mixed answers for whether or not the division operator "/" could be synthesized for constant values that are not a power of 2 so I went ahead and tried it using Synopsys Design Vision. It turns out that it does synthesize; however, I don't know how to check exactly how the final synthesized design functions or what it looks like (not sure if that's even possible). My question specifically is can I check the final logic synthesis at the gate level to see how it implements "/" division, and if not can anybody help shed light as to what it is probably doing (i.e., is it implementing a combination of shifts and addition/multiplication?).
For context, I am just implementing a module that solves for the first 3 terms of the taylor series expansion for sin and cos, like this:
reg [31:0] x, x_2, x_3, x_4, x_5;
reg signed [31:0] term1, term2, term3, term4, term5;
...
term1 = 1 << 16; // Q16.16 format
term2 = x_2 / 2; // x terms also already converted to Q16.16
term3 = x_4 / 24;
cos_sum = term1 - term2 + term3;
The sin version uses a similar flow with different terms and division constants. I've left out some stuff like calculations for x^(0, 1, 2, etc.). The code has also passed my testbench with inputs of -45 to 45 degree inputs as well. Just figured I'd share in case it helps provide context to figure out how Design Vision does the synthesis.
2 ** 32 / 24using the correct rounding. Not sure if you can get any deeper understanding than that. Maybe you need a more "interesting" example to reverse-engineer synthesized design.x_4 / 24is the same as(x_4 >> 3) / 3. The>> 3is basically a no-logic and most tools can handle divide by 3. It becomes trickier with larger divisors after the 2s been factor out. And even more challenging when the divisor is dynamic (ex24 / x_4). FPGA and ASIC synthesizers usually have some predefined modules for arithmetic logic for their specific platform, but might not meet all needs.