Using Quartus IP Catalog, how can I get predefined module name and ports order?

Question

For the code below, I utilized a predefined RAM module from Quartus to create the RAM. How do I determine the port order when instantiating it?

I understand it must be compatible with the module from which it's instantiated, but how can I ascertain the correct port order for the predefined module?

ram32x4 U1 (Address, Clock, DataIn, Write, DataOut);

// This code instantiates a 32 x 4 memory 
//
// inputs: KEY0 is the clock, SW3-SW0 provides data to write into memory.
// SW8-SW4 provides the memory address, SW9 is the memory Write input.
// outputs: 7-seg displays HEX5-4 show the memory address, HEX2
// displays the data input to the memory, and HEX0 show the contents read
// from the memory. LEDGR shows the status of the SW switches.
module part2 (KEY, SW, HEX5, HEX4, HEX2, HEX0, LEDR);
    input [0:0] KEY;
    input [9:0] SW;
    output [0:6] HEX5, HEX4, HEX2, HEX0;
    output [9:0] LEDR;

    wire Clock, Write;
    wire [4:0] Address;
    wire [3:0] DataIn, DataOut;

    assign Clock = KEY[0];
    assign Write = SW[9];
    assign DataIn = SW[3:0];
    assign Address = SW[8:4];

    // instantiate memory module
    // module ram32x4 (address, clock, data, wren, q);
    ram32x4 U1 (Address, Clock, DataIn, Write, DataOut);

    // display the data input, data output, and address on the 7-segs
    hex7seg digit0 (DataOut[3:0], HEX0);
    hex7seg digit2 (DataIn[3:0], HEX2);
    hex7seg digit5 ({3'b0, Address[4]}, HEX5);
    hex7seg digit4 (Address[3:0], HEX4);

    assign LEDR[3:0] = DataIn;
    assign LEDR[8:4] = Address;
    assign LEDR[9] = Write;
endmodule

// the B input blanks the display when B = 1
module hex7seg (hex, display);
    input [3:0] hex;
    output [0:6] display;

    reg [0:6] display;

    /*
     *       0  
     *      ---  
     *     |   |
     *    5|   |1
     *     | 6 |
     *      ---  
     *     |   |
     *    4|   |2
     *     |   |
     *      ---  
     *       3  
     */
    always @ (hex)
        case (hex)
            4'h0: display = 7'b0000001;
            4'h1: display = 7'b1001111;
            4'h2: display = 7'b0010010;
            4'h3: display = 7'b0000110;
            4'h4: display = 7'b1001100;
            4'h5: display = 7'b0100100;
            4'h6: display = 7'b0100000;
            4'h7: display = 7'b0001111;
            4'h8: display = 7'b0000000;
            4'h9: display = 7'b0000100;
            4'hA: display = 7'b0001000;
            4'hb: display = 7'b1100000;
            4'hC: display = 7'b0110001;
            4'hd: display = 7'b1000010;
            4'hE: display = 7'b0110000;
            4'hF: display = 7'b0111000;
        endcase
endmodule

The code is working correctly, but from where can we get the predefined module name and ports order?

There are two ways to generate RAM. You can code it (inferred ram) or you can use the IP tool. The IP tool makes 'simulation files'. You can look at the simulation file to know the parameters. Can you explain this *predefined RAM module * in more detail? Ok, the title clarifies. You use the IP tool. Have it generate simulation files. Look for a sub-directory where the project file is located. — artless-noise-bye-due2AI
– artless-noise-bye-due2AI, Commented Apr 4 at 14:02

toolic · Accepted Answer · 2025-03-05 20:20:29Z

The instance port connections you use in this line:

ram32x4 U1 (Address, Clock, DataIn, Write, DataOut);

are connection-by-order. However, that is a common Verilog pitfall which is prone to human error. A better way to create a module instance is to use connections-by-name. Assuming the module port names are what you posted in this comment:

// module ram32x4 (address, clock, data, wren, q);

then the way to create this instance is like this:

ram32x4 U1 (
    .address(Address), 
    .clock  (Clock), 
    .data   (DataIn), 
    .wren   (Write), 
    .q      (DataOut)
);

While this style is more verbose, it allows you to make the connections in any order. For example, you could place q first:

ram32x4 U1 (
    .q      (DataOut),
    .address(Address), 
    .clock  (Clock), 
    .data   (DataIn), 
    .wren   (Write)
);

Refer to IEEE Std 1800-2023 section 23.3.2.2 Connecting module instance ports by name.

See also: Verilog: How to instantiate a module

Collectives™ on Stack Overflow

Using Quartus IP Catalog, how can I get predefined module name and ports order?

1 Answer 1

Comments

Your Answer

Linked

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Linked

Related