What are the differences between using hierarchical names and port declarations?

Question

In Verilog, you can declare wires/registers

as ports and connect them at instantiation (port_A in example)
as ports and connect them "later"/"outside" using hierarchical names (port_B in example)
private and still connect them using hierarchical names (internal_ in example)

Example:

module SubModule (
    input wire in_port_A,
    output wire out_port_A,
    input wire in_port_B,
    output wire out_port_B
);
    wire internal_wire;
    reg internal_reg = 0;
    assign out_port_A = in_port_A;
    assign out_port_B = in_port_B;
endmodule

module Test;
    reg A = 0;
    wire a;
    reg B = 0;
    wire b;
    reg I = 0;
    wire i;
    wire r;
    
    SubModule sub(
        .in_port_A(A),
        .out_port_A(a)
    );
    
    assign sub.in_port_B = B;
    assign b = sub.out_port_B;
    
    assign sub.internal_wire = I;
    assign i = sub.internal_wire;
    
    assign r = sub.internal_reg;
    
    
    initial begin
        $display ("a: %0b", a);
        A = 1;
        $display ("a: %0b", a);
        
        $display ("b: %0b", b);
        B = 1;
        $display ("b: %0b", b);
        
        $display ("i: %0b", i);
        I = 1;
        $display ("i: %0b", i);
        
        $display ("r: %0b", r);
        sub.internal_reg = 1;
        $display ("r: %0b", r);
        
    end
endmodule

Output:

a: 0
a: 1
b: 0
b: 1
i: 0
i: 1
r: 0
r: 1

What are the differences between these methods? Is declaring them as ports merely to convey the intention of "this should be used/connected outside"?

I would add (1) steer clear of hierarchical names except for debug purposes, and (2) remember that port directions are advisory and may not be enforced by the tools. Also, it pays not to over-think Verilog. It wasn't 'designed' in the same way as other languages and large parts of it are fairly ad-hoc. — EML
– EML, Commented Mar 23 at 9:22

toolic · Accepted Answer · 2025-06-27 16:26:07Z

1

Yes, connecting instance ports directly better conveys the design intent. It is also a more compact syntax, and it is easier to understand the design.

It also avoids compiler warnings, which I get with 2 different simulators.

If you want to synthesize the design, synthesis tools may not support the hierarchical style.

Note: Due to a simulation race condition in your code, the output you show is not guaranteed.

edited Jun 27 at 16:26

answered Mar 20 at 11:11

toolic

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Spekboom07 · Accepted Answer · 2025-03-20 11:06:51Z

0

Ports

Declared as inputs/outputs; define the module’s external interface.
Connected during instantiation.

Hierarchical Connections:

Access internal signals (wires/registers) via the module instance (e.g. sub.internal_wire).
Useful for debugging but break encapsulation.

Private Internal Signals:

Meant solely for internal module logic.
Should not be accessed externally, even if possible via hierarchical names.

Ports are for the intended external interface, while hierarchical access (of internal signals) is a hack for debugging or special cases. Private signals are internal and should remain so.

answered Mar 20 at 11:06

Spekboom07

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