No expected result when using Vivado. What's the problem with the testbench file?

There are 2 types of major problems with the testbench code:

1. Verilog syntax errors
2. None of the inputs are driven

If Vivado did not show multiple syntax errors (compile errors) with your testbench code, then there is a problem with the simulator. You can try to compile your code on other simulators on EDA Playground to see these errors yourself.

I posted new code that compiles below. Refer to the commented-out lines to see which lines are problematic.

Once the syntax errors are fixed, the other problem was that you did not drive any of the input signals to the counter module. Since you declared all these signals as reg types, they default to the unknown value x. You need to initialize them to known values (0 or 1). I added that code inside the initial block. This code will get you started:

`timescale 1ns / 1ps

//module behav_counter();
module tb();

reg   [7:0] d;
reg   clk;
reg   clear;
reg   load;
reg   up_down;
wire  [7:0] qd;
reg     [7:0] cnt;
//always @ (posedge clk)

always #10 clk = !clk;

//behav_counter.a1(
behav_counter a1(
    .d(d),
    .clk(clk),
    .clear(clear),
    .load(load),
    .up_down(up_down),
    .qd(qd)
//    .qd(qd),
//    .cnt(cnt),
);

initial begin
    clk = 0;
    clear = 1;
    load = 1;
    up_down = 0;
    d = 5;
    #500 $finish;
end
endmodule

Now the clock toggles and the counter is loaded with 5.