I'm trying to do some operations in a Xilinx FPGA. Here is my code. When i simulate the code, the error validation signal does not assert. i need the signal to allow the next step of operations to continue
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PID_float is
Port (clk: in std_logic;
rst: in std_logic;
arst: in std_logic;
PID_start: in std_logic;
adc_in: in std_logic_vector(31 downto 0);
adc_valid: in std_logic;
ref: in std_logic_vector(31 downto 0);
ref_valid: in std_logic;
kp: in std_logic_vector(31 downto 0);
kp_valid: in std_logic;
PID_OUTPUT: out std_logic_vector(31 downto 0)
);
end PID_float;
architecture Behavioral of PID_float is
COMPONENT floating_point_0
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT floating_point_1
PORT (
aclk : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal error_fvalid: std_logic := '0';
signal error: std_logic_vector(31 downto 0) := (others => '0');
signal prop_valid: std_logic := '0';
signal prop: std_logic_vector(31 downto 0) := (others => '0');
begin
subtractor_error_inst : floating_point_0
PORT MAP (
aclk => clk,
aresetn => arst,
s_axis_a_tvalid => ref_valid,
s_axis_a_tdata => ref,
s_axis_b_tvalid => adc_valid,
s_axis_b_tdata => adc_in,
m_axis_result_tvalid => error_fvalid,
m_axis_result_tdata => error
);
proportional_multiplication : floating_point_1
PORT MAP (
aclk => clk,
s_axis_a_tvalid => kp_valid,
s_axis_a_tdata => kp,
s_axis_b_tvalid => error_fvalid,
s_axis_b_tdata => error,
m_axis_result_tvalid => prop_valid,
m_axis_result_tdata => prop
);
process(clk,rst,prop_valid)
begin
PID_OUTPUT <= prop;
end process;
end Behavioral;
`
test bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PID_float_tb is
-- Port ( );
end PID_float_tb;
architecture Behavioral of PID_float_tb is
component PID_float is
Port (clk: in std_logic;
rst: in std_logic;
arst: in std_logic;
PID_start: in std_logic;
adc_in: in std_logic_vector(31 downto 0);
adc_valid: in std_logic;
ref: in std_logic_vector(31 downto 0);
ref_valid: in std_logic;
kp: in std_logic_vector(31 downto 0);
kp_valid: in std_logic;
PID_OUTPUT: out std_logic_vector(31 downto 0)
);
end component;
signal clk,rst,arst,adc_valid,ref_valid,PID_start,kp_valid: std_logic := '0';
signal adc_in, ref,kp, PID_OUTPUT: std_logic_vector(31 downto 0) := (others => '0');
begin
pid_test_inst: PID_float port map(clk => clk,
rst => rst,
arst => arst,
PID_start => PID_start,
adc_in => adc_in,
adc_valid => adc_valid,
ref => ref,
ref_valid => ref_valid,
kp => kp,
kp_valid => kp_valid,
PID_OUTPUT => PID_OUTPUT);
clk_process: process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5ns;
end process;
unit_test: process
begin
wait for 50ns;
rst <= '0';
arst <= '0';
ref <= "01000110101100111011000000000000";
adc_in <= "01000110100111000100000000000000";
kp <= "01000110011101000001110000000000";
wait for 10ns;
adc_valid <= '1';
ref_valid <= '1';
kp_valid <= '1';
end process;
end Behavioral;
I can see that the data is subtracted and multiplied. However, i still need the signal to activate future operations.
