I'm working on coding an I2C Master module in Verilog using the Zybo Z7-10 board. My goal is to control the SSD1306 OLED driver via I2C communication. As far as I can tell, my timing diagram fully complies with the I2C protocol, but the OLED is not functioning as expected.
In my timing diagram 1, I use a state machine where:
c_state = 0: IDLE
c_state = 1: START
c_state = 2: SEND_ADDR (currently sending 0x3C)
c_state = 3: WR_CMD (currently sending 0)
c_state = 4: ADDR_ACK
c_state = 5: SEND_DATA
c_state = 6: DATA_ACK
c_state = 7: STOP
Although it’s not shown in the attached timing diagram, SEND_DATA and DATA_ACK repeat continuously until the SSD1306 initialization and pixel data transmission are fully completed. Once all data is sent, c_state changes to STOP, and the communication ends when SDA transitions from 0 to 1 while SCL is high.
The SEND_DATA and DATA_ACK states are designed to repeat continuously in a loop. I suspect that the continuous repetition of SEND_DATA and DATA_ACK might be causing the issue, but I'm not entirely sure.
I'm using the JE PMOD port on the Zybo Z7-10 board, and my XDC constraint file is as follows:
##Pmod Header JE
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { SCL_0 }]; #IO_L4P_T0_34 Sch=je[1]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { SDA_0 }]; #IO_L18N_T2_34 Sch=je[2]
set_property PULLUP TRUE [get_ports SDA_0];
set_property PULLUP TRUE [get_ports SCL_0];
If anyone notices any problems in my design, I would greatly appreciate your feedback.
