2

In Quartus II it was possible to make a flexible RAM component with a little "generic" modification to a SINGLE file generated by MegaWizzard manager. So it was so easy and fast to add several extra RAMs to debug architecture.

ENTITY RAM_JTAG_mf IS
    GENERIC(
    RAM_hint : string := "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NAME";
    RAM_reg_width   : positive  := 8;
    RAM_addr_width  : positive  := 10;
    RAM_init_name   : string    := "./ADS_RAM_file.mif"
    );
    PORT(
    address     : IN STD_LOGIC_VECTOR (RAM_addr_width-1 DOWNTO 0);
    clock       : IN STD_LOGIC  := '1';
    data        : IN STD_LOGIC_VECTOR (RAM_reg_width-1 DOWNTO 0);
    wren        : IN STD_LOGIC ;
    q       : OUT STD_LOGIC_VECTOR (RAM_reg_width-1 DOWNTO 0)
    );
END RAM_JTAG_mf;

Is it possible something similar in Quartus Prime (25.1 in particular)?

I've tried to find where these parameters are initialized. Unfortunately, there are at least three files including .ip, .v and .vhd (for my VHDL language choice). Creating a new IP component (with all related files and folder) via IP configuration tool for each new RAM seems terribly inefficient.

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