In Vivado, what is "[Synth 8-7213] Expression condition using operand 'x' does not match with the corresponding edges used in event control" error?

Question

When I am doing some development with Verilog and Vivado, I wrote some Verilog code as follows:

module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED);
    always @(posedge clk or negedge rst_n)
    begin
        if(rst_n)
        begin
            LED <= {LED[0], LED[3:1]};
        end
        else
        begin
            LED <= 4'b0000;
        end
    end
endmodule

But when I try to synthesize it, it reports this error:

[Synth 8-7213] Expression condition using operand 'rst_n' does not match with the corresponding edges used in event control"

and synthesis failed.

And expression with ? : operator is the same:

module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED);
    always @(posedge clk or negedge rst_n)
    begin
        LED <= rst_n? LED{LED[0], LED[3:1] : 4'b0000;
    end
endmodule

If I change the rst_n to !rst_n, the Verilog code works as expected with no errors:

module min_rep_example_B(input clk, input rst_n, output reg[3:0] LED);
    always @(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
        begin
            LED <= 4'b0000;
        end
        else
        begin
            LED <= {LED[0], LED[3:1]};
        end
    end
...

And so it is with ? : operator:

module min_rep_example_B(input clk, input rst_n, output reg[3:0] LED);
    always @(posedge clk or negedge rst_n)
    begin
        LED <= (!rst_n)? 4'b0000 : LED{LED[0], LED[3:1];
    end
endmodule

What is the reason and why rst_n usage reports synthesis error and !rst_n usage will work?

This is a minimal reproducible example. And because it is "minimal" reproducible example, I directly use "clk" as signal name, it may be slower and may not directly binding to hardware clk (such as 50MHz).

toolic · Accepted Answer · 2025-07-09 22:15:39Z

Synthesis tools require the Verilog code to match specific patterns in order to map the RTL style code to known logic gate constructs. The problem with your original code is that it does not match any known patterns supported by the synthesis tool. In other words, the example_A code does not follow the rules of your synthesis tool. This is what the error message means.

The sensitivity list does not match the reset condition. In the sensitivity list, it looks like you intend to infer an active-low reset, but in the condition, it looks like you intend to infer an active-high reset.

You second example (example_B) does adhere to the tool's supported patterns:

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)

This code is consistent, and it properly models an asynchronous active-low reset:

negedge rst_n
if(!rst_n)

This code properly describes 4 flip-flops triggered off the positive edge of the clock and asynchronously reset to 0 on the falling edge of the reset signal. The code simulates that way, and the synthesis tool will infer that logic.

Refer to synthesizable constructs.

example_A code does not simulate that way, and as you know, it results in a synthesis error. Refer to the Vivado documentation for further details about the error message.

You should avoid the ternary operator there because I don't think it is supported by many synthesis tools; prefer the if/else syntax when inferring an asynchronous reset.

EML · Accepted Answer · 2025-07-13 09:35:11Z

You have two conditions for running your always block: posedge clk, or negedge rst_n. In Verilog, the code in your always block can't tell which condition actually caused the block to 'run'.

Your first test is if(rst_n). Now, you're smart enough to know that if this is true, the block must be running because there was a clock edge. So, as far as you (and the simulator) are concerned, the code clears LED if rst_n is 0, and otherwise rotates LED.

A synthesiser doesn't run your design, and works by template matching, and your code is just confusing it. The clue is in the error message: "Expression condition using operand 'rst_n' does not match with the corresponding edges used in event control". IOW, it's looking for a test that rst_n is low. This isn't actually an "error", but the synth doesn't know what to do, so gives up.

See here for basic templates and coding styles which you can use for sim and synth.

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