Is `x==1'bx` in Verilog?

Question

In Verilog, $display("%b",^ 3'b10x); outputs x.

As x==1'dx, I believe ^ 3'b10x==1'bx is true, but the result is false.

What's the correct result of ^ 3'b10x?

And why is ^ 3'b10x==1'bx false?

mkrieger1 · Accepted Answer · 2025-08-10 20:35:33Z

1

You have an operator precedence confusion. == binds tighter than ^, so your expression is interpreted as ^ (3'b10x==1'bx). Unexpected, perhaps, but those are the rules:

https://documentation-rp-test.readthedocs.io/en/latest/tutorfpga04.html

edited Aug 10 at 20:35

mkrieger1

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answered Aug 6 at 18:03

Tim Roberts

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