programming DDR to produces samples for RFSOC4x2 question

This is programming FPGA question so its both programming in C and hardware.Hope its suitable for this forum and If not I'll be glad to get a more suitable place to post this question. I am building a program that needs to write samples into DDR so on the output of the DAC I will see the output signal. At first I have built a block diagram in vivado shoWn in the link both as PDF and TCL file. Then I created and XSA file to use in VITIS and I found a code which is supposed to create 1.5GHz tone in my DAC. Could you please say its this code make sense? Is it properly writing samples to DDR so I could see the output voltage in the DAC? I'll be happy to have feedback regarding the code shown below. Thanks.

XSA file that I used:

XSA file link

tcl file of the BD:
TCL file link

pdf of the BD:

PDF file link

#include "xparameters.h"

#include "xil_printf.h"

#include "xaxidma.h"

#include "xil_cache.h"

#include <stdint.h>

#include <math.h>

/* AXI DMA device ID from xparameters.h */

#define DMA_DEV_ID XPAR_AXIDMA_0_DEVICE_ID

/* Baseband sample rate into the DAC DUC: 400e6 * 8 = 3.2e9 samples/s */

#define FS_BB_HZ 3200000000.0f

/* Desired RF tone (Zone-1) */

#define TONE_HZ 1500000000.0f /* 1.5 GHz */

/* Number of 16-bit samples in the repeating buffer (multiple of 8) */

#define N_SAMPLES 4096

/* Amplitude as fraction of full-scale (0.0..0.95). Start ~0.5 */

#define AMP_FS 0.5f

static int16_t TxBuf[N_SAMPLES] __attribute__((aligned(64)));

static XAxiDma AxiDma;

static void make_tone(void)

{

/* Choose an integer FFT bin so the buffer repeats seamlessly.

For Fs=3.2e9 and N=4096, bin spacing is 781250 Hz; 1.5 GHz => k=1920. */

const float k = roundf(TONE_HZ * (float)N_SAMPLES / FS_BB_HZ);

const float w = 2.0f * (float)M_PI * k / (float)N_SAMPLES;

const float A = AMP_FS * 32767.0f;

for (int n = 0; n < N_SAMPLES; ++n)

TxBuf[n] = (int16_t)lrintf(A * sinf(w * n));

}

int main(void)

{

xil_printf("\r\n[RFSoC DAC] 1.5 GHz tone via AXI-DMA (MM2S)\r\n");

XAxiDma_Config *cfg = XAxiDma_LookupConfig(DMA_DEV_ID);

if (!cfg) { xil_printf("DMA cfg not found\r\n"); return -1; }

if (XAxiDma_CfgInitialize(&AxiDma, cfg) != XST_SUCCESS) {

xil_printf("DMA init failed\r\n"); return -1;

}

if (XAxiDma_HasSg(&AxiDma)) {

xil_printf("This app expects SIMPLE mode DMA\r\n"); return -1;

}

make_tone();

const int bytes = N_SAMPLES * (int)sizeof(TxBuf[0]); /* multiple of 16 bytes */

while (1) {

Xil_DCacheFlushRange((INTPTR)TxBuf, bytes);

if (XAxiDma_SimpleTransfer(&AxiDma,

(UINTPTR)TxBuf,

bytes,

XAXIDMA_DMA_TO_DEVICE) != XST_SUCCESS) {

xil_printf("DMA submit failed\r\n"); return -1;

}

while (XAxiDma_Busy(&AxiDma, XAXIDMA_DMA_TO_DEVICE)) { }

}

return 0;

}

I tried to learin the logic of this code . I am expecting it to enable the DAC to output voltage values according to the software. Thanks.