Unresolved reference to 'fulladder' in Verilog

Question

I am having some issues when attempting to run a simulation. It seems there is an issue with my instances of my first 2 modules inside of my 3rd module. The code is compiling okay, but I am running into trouble when I try to run a simulation.

I am not really sure if the problem is in my code or my test bench.

module fulladder
(
 input [15:0] x,
 input [15:0] y,
 output [15:0] O 
 );
 
assign O =   y + x;
 
endmodule

module shifter
(
 input [15:0] in,
 input [2:0] N,
 output [15:0] O 
 );
  reg [7:0] out_reg;
  assign O = out_reg;

  always @(N or in) begin
    case (N)
      7 : out_reg <= { in[7:0],7'b0};
      6 : out_reg <= { in[7:0],6'b0};
      5 : out_reg <= { in[7:0],5'b0};
      4 : out_reg <= { in[7:0],4'b0};
      3 : out_reg <= { in[7:0],3'b0};
      2 : out_reg <= { in[7:0],2'b0};
      1 : out_reg <= { in[7:0],1'b0};
      0 : out_reg <=         in[7:0];
    endcase
  end

endmodule

module my_multiplier(Rst, Ld, clk, A, B, O);
input clk;
input [7:0]A, B;
input Rst, Ld;
output [15:0] O;
reg Done;
reg [15:0] Otemp;
reg [15:0] O;
reg [7:0] Atemp;
reg [1:0] state;
reg [1:0] C;

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

always @(posedge clk or posedge Rst)
begin
   case(state)
    S0: begin
    Done <= 0;
    if (Ld == 1)
    begin
       C <= 0;
       Atemp <= A;
       state <= S1; 
    end
    else
       state <= S0; 
    end

    S1: if (B[C] == 1) 
    begin
       shifter ( A, C, Atemp);
       O <= Otemp;
       C <= C + 1;
       state <= S2; 
    end
    else 
    begin
       Atemp <= 0;
       O <= Otemp;
       C <= C + 1;
       state <= S2; 
    end
    S2: begin
    O <= Otemp;
    if (C == 3)
      state <= S3;
    else
      state <= S2;
    end
    S3:  begin
        Done <= 1;
    state <= S0;
    end
    default 
    state <= S0;

   endcase

   fulladder (Atemp, O, Otemp);

end   

endmodule


module my_multiplier_tb;

reg clk_tb;
reg [7:0]A_tb, B_tb;
reg  Rst_tb, Ld_tb;
wire [15:0] O_tb;

my_multiplier dut( Rst_tb, Ld_tb, clk_tb, A_tb, B_tb, O_tb );

always #5 clk_tb = ~clk_tb;

initial begin
  A_tb = 8'd8;  
  B_tb = 8'd7;

  #15 Ld_tb = 1; // set Load to begin multiplication
  #10 Ld_tb = 0; // wait 1 clock cycle
  #300   

  $monitor($time, "\t A=%d,\t B=%d,\t O=%d", A_tb, B_tb, O_tb);
    
  $finish;
end

endmodule

toolic · Accepted Answer · 2021-10-13 17:58:33Z

0

The problem is in the my_multiplier module where you have multiple syntax errors. If you sign up for a free account on edaplayground and post your code there, you may see more helpful compile errors there.

You must not place a module instance inside an always block. These 2 lines must be moved outside the always:

fulladder (Atemp, O, Otemp);
shifter ( A, C, Atemp);

Once you do that, you need to add instance names, like i0 and i1 below:

fulladder i0 (Atemp, O, Otemp);
shifter i1 ( A, C, Atemp);

edited Oct 13, 2021 at 17:58

answered Oct 10, 2021 at 14:19

toolic

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