233 questions
0
votes
2
answers
107
views
Why doesn't a Wallace tree produce numbers with more than 2n final product bits?
I am trying to understand Wallace Trees.
The algorithm goes
multiply each bit of one number a by each bit of the other (b), which is accomplished as a simple AND gate, where the partial product of ...
- 641
0
votes
0
answers
60
views
How to fix State <name> contains multiple transitions, but more than one transition equation are TRUE when <text> in Quartus?
I'm trying to develop a Elevator FSM machine in quartus in order to get his equivalent to HDL code. The FSM is this:
But when I set the Input, transitions and output in "State Machine Wizard&...
- 71
1
vote
1
answer
94
views
In a testbench, is there a way to see the internal declared regs/wires of a module without having to connect them to ports?
Let's say we're trying to write a Verilog/SystemVerilog testbench code named SC_TB for module sample_code. Is there a more practical way of seeing what reg B and wire Cw is doing in testbench, without ...
- 13
0
votes
0
answers
87
views
How can I transform yosys gate primitives (e.g. $reduce_or) to simple gates and then pattern match those to more complex Verilog cells?
I am new to Yosys, and I want to optimize arbitrary netlists to a set of complex cells.
For example's sake, let's consider an or-reductions:
red_or3x1_test.v
module test (A, Y);
input [6:0] A;
...
- 11
1
vote
1
answer
95
views
How to make multiplexer with functions?
My assignment is to create a multiplexer given a table. So far, this is what I have. A and B are 4-bit inputs via toggle switch, S is the MUX controller, Cin is a carry-in that we assign a toggle ...
- 11
-1
votes
1
answer
347
views
D-type Flip Flop - Behavioral vs Gate-Level Modeling in Verilog, Timing of state transitions
Modeling a D-type Flip Flop in Verilog with gate-level modeling vs. behavioral modeling seems to result in state transitions happening at different edges of the clock signal. I'm sure I'm missing ...
- 1
1
vote
1
answer
138
views
Parameter Overriding
How and where do I perform parameter override to this question?
While I try to override it using #, I am receiving a warning stating that the port size does not match to the inputs and outputs or the ...
- 11
0
votes
1
answer
569
views
How can I implement the overflow flag in Logisim without having access to the second last carry?
In the pic of the ALU, I've implemented the logic to calculate the zero, negative and carry flags. But I can't figure out how to implement the overflow flag without using the second last carry (carry-...
0
votes
1
answer
127
views
designing a circuit with 3 3-bit inputs and 4 1-bit outputs
The inputs are A[2:0], B[2:0] and C[2:0] respectively. The outputs are E,RA,RB,RC.
If at least at one of the inputs (A,B,C) none of the bits are equal to 1 or if at least at one input the bits that ...
- 1
0
votes
1
answer
321
views
How to mitigate / suppress tristate bus conflict warnings with Cocotb?
I am using cocotb to simulate a large SystemVerilog design.
When I run the simulation, I see a very large number of log warnings of the form:
[timestamp] ++BUS CONFLICT++ : top.submodule1.submodule2....
- 101
-1
votes
1
answer
140
views
FPGA Basys 3 State Machine Logic with PMOD ALS Sensor
For a lab I must create the logic to use on a Digilent PMOD ALS. In the lab requirenment I cannot use the sclk signal on the sensitivity list and therefore use a state machine to create the 2.5 MHz ...
- 1
-2
votes
4
answers
152
views
Understanding the functioning of 'and' and 'or'
Here's a doubt I am facing here.
The code with its purpose in docstring is below :
This is the correct code but I am confused about the final 'if statement' in the blackjack_hand_greater_than(a,b) ...
- 3
1
vote
2
answers
222
views
How can I determine the sop and pos part from a combined expression
𝐹(𝐴, 𝐵, 𝐶, 𝐷) = (𝐷′ + 𝐴𝐵′)(𝐴𝐷 + 𝐶′)𝐵′ + 𝐵𝐷′(𝐴′ + 𝐶′) + 𝐴′
like this combined expression where SOP and POS are both available how can I know which are sop & which are pos?
I am ...
- 11
0
votes
1
answer
1k
views
width mismatch in assignment; target has 10 bits, source has 8 bits error
I try to write VHDL code in Vivado to show multiply 8 bit number by 1,2,3,4.
i got the error in line (y <= ..) :
" width mismatch in assignment; target has 10 bits, source has 8 bits error in ...
- 1
1
vote
3
answers
783
views
Using One's Complement In Place of Directly Subtracting Two Binary Numbers
I've decided to start learning some logic design recently. I'm current at the very first unit in the book I'm using (Fundamentals of Logic Design - 5th Edition if it's of any importance) and it's ...
0
votes
1
answer
405
views
How to write ALU control lines?
I know logical ADD in binary is 0010, and logical AND in binary is 0000. How do I go from this to a full operation?
- 58
0
votes
2
answers
91
views
Multiplication table in VMLab / AVR
I am trying to figure out this question. I posted my code below. It doesn't work properly. it seems like its not multiplying the 2 least significant nibbles. I don't know AVR very well.
Write AVR that ...
- 1
0
votes
1
answer
376
views
VHDL - Upper digit output does not go up from '0000', when implementing two-digit-bcd-counter
I'm trying to implement two-digit-bcd-counter in VHDL, by referring to this diagram:
This is my code for it:
library ieee;
use ieee.std_logic_1164.all;
entity two_digit_bcd_counter is
port(
v_cc ...
- 165
0
votes
2
answers
386
views
Output not as expected when implementing 4-bit SISO register in VHDL
I am trying to create a 4-bit SISO register in VHDL, and this is my main code:
library ieee;
use ieee.std_logic_1164.all;
entity right_shift_siso_reg_4 is
port(
D_in : in std_logic;
clk : ...
- 165
1
vote
1
answer
704
views
Problem while implementing JK-Flip Flop in VHDL
I'm trying to implement JK flip-flop in VHDL, and here is my code:
library ieee;
use ieee.std_logic_1164.all;
entity jk_flip_flop is
port(
J, K : in std_logic;
clk : in std_logic;
...
- 165
0
votes
1
answer
459
views
How to represent multiple-output logic circuits in tree-based genetic programming
Consider the following digital logic circuit, which has multiple inputs and one output:
The logic circuit above can be represented in tree form:
This tree representation could then be used in a tree-...
- 11.1k
0
votes
1
answer
71
views
What does the double slash(transition 0 --> 1) mean in SRAM datasheet?
The following image is from the datasheet of SRAM IS64WV51216BLL(page 15).
It is a SRAM's write timing diagram.I don't know the meaning of double transitions for WE signal.I have circled it in red.
...
- 5
1
vote
1
answer
401
views
How to create K-MAP from function
How can I create a K-MAP by looking at this function.I dont know how to create one
- 1,170
0
votes
1
answer
1k
views
How can w’xz + w’yz + x’yz’ + wxy’z be implemented with 4 NOR gates (+ inverters), given d = wyz
How can you implement the following function with only four NOR gates and inverters:
F = w’xz + w’yz + x’yz’ + wxy’z
d = wyz
0
votes
1
answer
2k
views
Shifting in Verilog for multiplication
How does this line of code below works as the multiplication of (1024-31)?
The code is intended to be synthesized for FPGA, so shifting is used instead of direct division.
But what I do not understand ...
- 129
1
vote
1
answer
289
views
Capturing the right posedge clock in Quartus waveform
I am using Quartus Prime Lite 19.1.0.
module memory_address_register1 #(
parameter ADDR_WIDTH = 4
)(
input clk, rst, load,
input [...
- 129
1
vote
0
answers
95
views
VHDL State Machine Skipping Intermediate State
I am trying to implement the controller for a simple CPU in VHDL. The controller is modeled as an ASM that waits in a decode state until it receives the start signal. The next state that it progresses ...
- 135
0
votes
1
answer
1k
views
D-latch time diagram with preset and clear?
I'm trying to study for an exam and I've been searching for any videos or images or pages explaining the time diagram for the D-Latch that involves the preset and clear. I'm finding a lot of results ...
user16951674
0
votes
1
answer
668
views
Verilog Binary Coded Decimal Adder Not Outputting Correctly
I'm new to Verilog and basically trying to teach myself a Digital Logic Design module for university. I am trying to write a BCD Adder in Verilog using two Full Adders with some logic in between for ...
1
vote
1
answer
2k
views
ALU using modules in Verilog
I am implementing a 4-bit ALU using Verilog.
I am getting some weird results in testbecnh.
Here is code for the ALU:
`include "ripple_carry_adder_4.v"
module alu_4(A, B, CTRL, Y);
...
- 11
4
votes
1
answer
933
views
How to simulate output delay using next_trigger() in SystemC?
I have been reading this upvoted answer on Stack Overflow: https://stackoverflow.com/a/26129960/12311164
It says that replacing wait(delay, units); in SC_THREAD to next_trigger(delay, units) in ...
user12311164
-2
votes
1
answer
139
views
Encoder number of outpus for opcode within a MIPS machine instruction
If I have an encoder with 8 data inputs, what is its maximum number of outputs?
I know that an encoder is a combinational circuit that performs the reverse operation of a decoder. It has a maximum of ...
- 101
1
vote
1
answer
661
views
2's complement std_logic_vector to unsigned number
I have a 4 bits std_logic_vector whose values are represented in 2's complement. And I want to extract it's unsigned value
signal FOURbits_2scomplement : std_logic_vector(3 downto 0);
signal ...
- 322
3
votes
1
answer
7k
views
How to create boolean data type to standard logic in VHDL
Is there an existing function within the regular std.logic library to convert a boolean data type to std logic in vhdl?
0
votes
1
answer
383
views
How to simplify sequential logic design by eliminating nested if-else statements
I have a design I've implemented using vhdl that is triggered based on a clock that sends an input signal to one of 8 output channels based on the sel input and also another 2 bit input. The ...
1
vote
0
answers
310
views
Register values not showing at the correct time in testbench simulation
Based on research, the input value to a flip flop is read during one rising/falling edge and output at the next rising/falling edge, however, I'm not seeing this behavior in my test bench.What I ...
-8
votes
1
answer
78
views
I don't understand how to do this Lesson :'(
Lesson 2: Design an address decoder for 64 KB memory from 16KB memory ICs, knowing that the memory base address is 94000H and the address decoder is designed using circuits combinatorial logic.
- 1
0
votes
1
answer
995
views
If the PC register is simultaneously read and written, does its read data contain the previous data or the newly-written data?
If the PC register is simultaneously read and written, does its read data contain the previous data or the newly-written data? Based on my understanding of sequential circuits, the effect of the write ...
- 83
0
votes
1
answer
817
views
Yosys synthesys - is this opimum?
I'm using yosys to synthesize simple circuits and show how the result varies with the cell library.
However, it looks like the result is not well optimized.
I'm using the library vsclib013.lib ...
- 43
1
vote
1
answer
265
views
Converstion from SOP to POS using boolean algebra
The question is this:
wx'y'+wyz'+w'x'z
I tried this technique but got stuck:
w(x'y'+yz')+w'x'z
(w+x'z)(w'+x'y'+yz')
(w+x')(w+z)(w'+x'y'+yz')
but this is not correct since it should end with 4 pos ...
0
votes
1
answer
125
views
How to simplify circuits
The answer to the question is A in case someone thinks Im cheating for a test or something. I really wan't to understand how to solve such questions. I am guessing there is some way to bring these ...
- 471
0
votes
1
answer
2k
views
Implementation of 8:1 MUX using 3:8 decoders and 2 input gates
How do I implement a 8:1 MUX using 3:8 decoders and 2 input gates?
I know how a 8:1 MUX works and how a 3:8 decoder works but I am not able to understand the approach to convert the decoder to mux ...
- 677
1
vote
2
answers
94
views
Chisel3 REPL Vec assignment into module only works after eval
If we run the following Chisel3 code
class Controller extends Module {
val io = IO(new Bundle {
})
val sff = Module(new SFF)
val frame: Vec[UInt] = Reg(Vec(ProcedureSpaceSize, Integer32Bit))
...
- 712
3
votes
1
answer
277
views
Chisel3 REPL peek value is correct but expect fails in test
I am using Chisel3 to build my circuit, and I have the following test
reset()
private val inputData = IndexedSeq.fill(ProcedureSpaceSize)(0: BigInt)
.patch(0, Seq(63: BigInt), 1)
.patch(1,...
- 712
3
votes
2
answers
537
views
How to test modules with bundle/vec input?
How do you test modules with IO input port of type Vec, Bundle, or composition of these?
In other words, using PeekPokeTester, how do you properly poke() a port that is of type Vec, Bundle, or more ...
- 712
0
votes
1
answer
39
views
C/Digital Logic - Why are my zero-initialized variables changing value?
They're actually initialized to the character '0' (ie 48). I'm making a logic simulator and each bit is represented as a single char, either '0' or '1'. All of my other components have worked until I ...
- 33
0
votes
1
answer
3k
views
How would you write a SystemVerilog Function that adds an even parity bit to a 7-bit vector?
Would you take a 7-bit logic variable as an input and return an 8-bit logic output with the parity bit being the MSB (leftmost bit) of the output?
In a system that uses even parity you want the total ...
2
votes
0
answers
901
views
Are there any "easy" fast algorithms for a 16 bit by 16 bit 2's complement integer divider?
I am currently working on a school project and one of my tasks is to implement a 16-bit by 16-bit 2's complement integer divider as a digital logic circuit (in other words 16-bit input divided by ...
1
vote
2
answers
13k
views
Two ways to write pipeline in verilog, which one is better?
I learned two ways of writing pipeline(unblocking and blocking), I wonder which is better?
My personal opinion is that the second one is tedious and I don't understand why so many wire are needed.
...
- 93
1
vote
0
answers
140
views
Smart way of simplifying logical circuits by hand?
Let's say I have the following logical circuit:
How can I create a simplified version (assuming that one exists) without laboriously creating a truth table for it? I was thinking of perhaps writing ...
- 1,791