233 questions
25
votes
4
answers
26k
views
Why were bitwise operations slightly faster than addition/subtraction operations on older microprocessors?
I came across this excerpt today:
On most older microprocessors, bitwise operations are slightly faster than addition and
subtraction operations and usually significantly faster than ...
- 12.1k
17
votes
3
answers
49k
views
What to use for VHDL/digital-logic simulation on Mac OS X
I suddenly realized that there is no Altera Quartus or Xilins ISE or ModelSim on Mac OS X.
What do people use to at least simulate VHDL and schematic designs on Macs?
- 14.4k
12
votes
10
answers
37k
views
Linear feedback shift register?
Lately I bumped repeatedly into the concept of LFSR, that I find quite interesting because of its links with different fields and also fascinating in itself. It took me some effort to understand, the ...
- 241
11
votes
4
answers
39k
views
What's included in a Verilog always @* sensitivity list?
I'm a bit confused about what is considered an input when you use the wildcard @* in an always block sensitivity list. For instance, in the following example, which signals are interpreted as inputs ...
- 749
10
votes
2
answers
7k
views
How CPUs implement Instructions like MUL/MULT?
In different assembly languages MUL (x86)/MULT (mips) refer to multiplication. It is a black box for the programmer. I am interested in how actually a CPU accomplishes a multiplication regardless of ...
- 15.7k
8
votes
1
answer
3k
views
How to handle loops in a digital logic simulator?
I'm developing a digital logic simulator to build my own CPU in it later (so it's a long term project). Everything works great for circuits with no loops, for example a fulladder. Then there are ...
- 123
6
votes
1
answer
22k
views
Using 2's Complement to Perform Binary Division for Signed Number
First of all, this is not a duplicate question of this because it hasn't answered my questions below.
I searched for many resources and ended with no clear perception of how to perform signed number ...
- 391
5
votes
1
answer
17k
views
How to use parameterized bitwidth for a constant value in Verilog?
Consider the following example:
parameter BITWIDTH = 16;
This works:
logic [1:0][BITWIDTH-1:0] var = {16'h30, 16'h40};
This doesn't work:
logic [1:0][BITWIDTH-1:0] var = {BITWIDTH'h30, BITWIDTH'h40}...
- 1,093
5
votes
2
answers
902
views
Digital Logic - Karnaugh Map
The initial problem starts like this. There are 6 states. At each state when w=1 move to the next state, when w=0 then stay at the current state. At each state display a number using a standard 7 led ...
- 227
4
votes
2
answers
3k
views
How does comparing the Sign and Overflow Flag determine operand relationships?
Jump's based on comparing signed integers use the Zero, Sign, and Overflow flag to determine the relationship between operands. After CMP with two signed operands, there are three possible scenario's:
...
- 377
4
votes
1
answer
933
views
How to simulate output delay using next_trigger() in SystemC?
I have been reading this upvoted answer on Stack Overflow: https://stackoverflow.com/a/26129960/12311164
It says that replacing wait(delay, units); in SC_THREAD to next_trigger(delay, units) in ...
user12311164
3
votes
2
answers
194
views
Right Shift in java
I am just stuck with this small logic that i am not getting it right
int is 32 bits so suppose taking 20 in binary would be like
// 00000000000000000000000000010100
.. now if I perform ...
3
votes
3
answers
14k
views
Why K-map has states in sequence of 00,01,11,10 instead of 00,01,10,11?
Why K-map has states in sequence of 00,01,11,10 instead of 00,01,10,11?
- 51
3
votes
2
answers
22k
views
not a valid l-value - verilog compiler error
module fronter ( arc, length, clinic ) ;
input [7:0] arc;
output reg [7:0] length ;
input [1:0] clinic;
input en0, en1, en2, en3; // 11
// clock generator is here
g_cal A( en0) ;
g_cal B( ...
user478571
3
votes
2
answers
745
views
Is I2C master to Master communication possible?
Is it possible for an I2C master device to communicate with another I2C master device ?
Thanks
- 55
3
votes
2
answers
537
views
How to test modules with bundle/vec input?
How do you test modules with IO input port of type Vec, Bundle, or composition of these?
In other words, using PeekPokeTester, how do you properly poke() a port that is of type Vec, Bundle, or more ...
- 712
3
votes
1
answer
8k
views
what is the operator precedence in Boolean algebra?
As a XOR b NOR c is not equal to a NOR b XOR c,there must be some precedence rule for all operators in Boolean algebra.So what is the precedence rule for XOR,NAND,XNOR,NOR ??
- 39
3
votes
1
answer
277
views
Chisel3 REPL peek value is correct but expect fails in test
I am using Chisel3 to build my circuit, and I have the following test
reset()
private val inputData = IndexedSeq.fill(ProcedureSpaceSize)(0: BigInt)
.patch(0, Seq(63: BigInt), 1)
.patch(1,...
- 712
3
votes
1
answer
351
views
Chisel synthesized none neither for verilog nor for C++
For the following fragment Chisel synthesized none:
import Chisel._
import Node._
import scala.collection.mutable.HashMap
class PseudoLRU(val num_ways: Int) extends Module
{
val num_levels = ...
3
votes
1
answer
918
views
Digital logic - mealy state machines?
I understand the way Mealy state machines work - the output logic is now a function of not just the current state but of the input directly as well.
But what is the advantage to this over Moore ...
- 17.2k
3
votes
1
answer
489
views
Difference between shift adder and Serial Adder
Is shift adder and serial adder are same? I tried Google but I cannot understand difference. I have to use it in VHDL.
Thanks
- 39
3
votes
1
answer
1k
views
It would be nice to have Vec[Mem] in Chisel
It would be nice to Vec[Mem] for say set-associative caches.
Unfortunately Chisel doesn't support Vec[Mem] construct:
val tag_ram2 = Vec.fill(num_ways) {Mem(new TagType(), num_sets , seqRead = ...
3
votes
1
answer
7k
views
How to create boolean data type to standard logic in VHDL
Is there an existing function within the regular std.logic library to convert a boolean data type to std logic in vhdl?
2
votes
2
answers
5k
views
Flip-flop and latch inferring dilemma
Could someone explain to me why a latch would be inferred instead of a flip-flop?
always_ff @ (posedge clk, negedge rst)
begin
if (!rst)
a <= '0;
end
Shouldn't the fact that the always ...
- 127
2
votes
2
answers
1k
views
Strange component in quartus RTL viewer using verilog
I'm learning verilog, and when i don't know how a circuit will work just looking in the verilog code, I go to RTL viewer to see the digital logic. But in this code a strange component appears and I ...
2
votes
2
answers
3k
views
Overflow and carry flag
The context
I read in a textbook that...
An addition and subtraction cannot cause overflow. To quote,
"An overflow cannot occur after an addition if one number is positive and the other negative,...
- 67
2
votes
1
answer
12k
views
Frequency divisor in verilog
i need a frequency divider in verilog, and i made the code below. It works, but i want to know if is the best solution, thanks!
module frquency_divider_by2 ( clk ,clk3 );
output clk3 ;
reg clk2, clk3 ...
2
votes
2
answers
13k
views
How to define clock input in Xilinx
Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to ...
- 1,531
2
votes
1
answer
2k
views
How is Carry Flag set when subtrahend is larger?
I know the Carry flag during SUB is set whenever the minuend is smaller than the subtrahend and a borrow is required, but haven't been able to find anything explaining this in more detail.
Since ...
- 377
2
votes
3
answers
507
views
K-Map to solve algebraic reduction
I need help verifying an algebraic expression using K-Map.
The expression I'm posting was actually done by my professor, but for practice purpose I wanted to use the K-Map to verify that the answer ...
- 306
2
votes
3
answers
21k
views
Structure of VHDL code for barrel shifter with behavior architecture
I am trying to build a 16 bit barrel shifter with left and right shift capabilities. I am having some issues with how to structure the code so that it will do what I think I want to do.
I have an ...
- 23
2
votes
4
answers
13k
views
Why Arduino digital pin output (`HIGH`, `LOW`) seem to be reversed?
I've written a sketch last year that worked well at that time. But now running this code results in reversed output (when HIGH is written to a digital pin it outputs LOW and vice versa).
// PROBLEM: ...
- 61
2
votes
1
answer
717
views
Chisel: how to avoid errors NO DEFAULT SPECIFIED FOR WIRE
I'm trying to implement a structured read port to Mem:
class TagType() extends Bundle()
{
import Consts._
val valid = Bool()
val dirty = Bool()
val tag = UInt(width = ADDR_MSB - ...
2
votes
2
answers
605
views
Is it possible to avoid specifying a default in order to get an X in Chisel?
The following Chisel code works as expected.
class Memo extends Module { ...
- 4,722
2
votes
1
answer
3k
views
Race conditions
I'm currently stuck trying to understand two things related to race conditions.
Issue 1:
I have been presented with the following question:
We consider the digital circuit and the value of its ...
- 13.3k
2
votes
1
answer
749
views
How would you handle a special case in this digital logic system?
I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA.
alt text ...
- 119k
2
votes
2
answers
16k
views
What is the maximum number of inputs for any logic gate?
In the references that we use, I usually see either a 2 or 3-input logic gate. Four-input gates come by once in a while. However, is there a certain limit to the number of inputs a logic gate can have ...
- 23
2
votes
1
answer
489
views
Chisel runtime error in test harness
This Chisel code works ok:
chiselMainTest(Array[String]("--backend", "c", "--genHarness"), () => Module( new Cache(nways = 16, nsets = 32) )){c => new CacheTests(c)}
However this one - a small ...
2
votes
1
answer
3k
views
Application of Barrel Shifter
I am doing a VLSI Project and I am implementing a Barrel Shifter using a tool called DSCH.The schematic for the same is realized using Transmission Gates.
What the circuit does is, it ROTATES the 8 ...
- 21
2
votes
0
answers
901
views
Are there any "easy" fast algorithms for a 16 bit by 16 bit 2's complement integer divider?
I am currently working on a school project and one of my tasks is to implement a 16-bit by 16-bit 2's complement integer divider as a digital logic circuit (in other words 16-bit input divided by ...
2
votes
1
answer
1k
views
Making K-maps with S2, S1, S0 (seven states), one button input, and four outputs
So my state diagram has seven states (000 to 110), an input B button, and four outputs P, Q, R, and S.
I've made the truth table, which has 16 rows (two of which have Xs). I'm supposed to make 7 K-...
- 63
2
votes
1
answer
3k
views
Verilog: Store counter value when reset is asserted
I have the following verilog code. Idea is to store value of counter at the time of reset. However, I am not sure if it would be synthesizable(memories need synchronous reset). I get DRC violatins and ...
- 582
1
vote
3
answers
9k
views
How to tell if an integer is signed or not?
How can I/computer tell if binary numbers are signed or unsigned integers?
Eg the binary number 1000 0001 can both be interpreted as -128, if signed, and 129, if unsigned.
One advantage of using ...
user3675996
1
vote
1
answer
22k
views
Use of wire inside an always block?
Can I use a wire inside an always block?
Like for example:
wire [3:0]a;
assign a=3;
always @(c)
begin
d=a+c;
end
It got compiled ...
- 185
1
vote
4
answers
688
views
Why does the number of bits in the binary representation of decimal number 16 == 5?
This question not probably not typical stackoverflow but am not sure where to ask this small question of mine.
Problem:
Find the number of bits in the binary representation of decimal number 16?
...
- 2,474
1
vote
1
answer
7k
views
Number of Prime Implicant and EPI
My TA solve this problem, Number of Prime Implicant (PI) for
f(a,b,c,d)= Sigma m(0,2,4,5,8,10,11,13,15)
is 7 and number of Essential PI (EPI) is 1. how this will be calculated? I think it's wrong. ...
user4591951
1
vote
5
answers
700
views
Digital Circuit understanding
In my quest for getting some basics down before I start going into programming I am looking for essential knowledge about how the computer works down at the core level.
I have a theory that actually ...
- 155
1
vote
3
answers
783
views
Using One's Complement In Place of Directly Subtracting Two Binary Numbers
I've decided to start learning some logic design recently. I'm current at the very first unit in the book I'm using (Fundamentals of Logic Design - 5th Edition if it's of any importance) and it's ...
1
vote
1
answer
267
views
What is the USART digital logic in AVR microcontrollers?
Just reading about USART connection in AVR microcontrollers and i faced this question:
What is the digital logic used in USART(RXC, TXC and other internals) of the AVR microcontrollers?
I've found ...
- 771
1
vote
2
answers
3k
views
Entity Instantiation Inside of a Process
I am trying to make a two dimensional array of full adders with specific logic with their inputs and outputs. I currently have two for-generate statements of rows and columns, and then an if-elsif-...
- 33