35 questions
1
vote
1
answer
145
views
Why does APB testbench not send data into the prdata register?
Here is my code on EDA Playground.
`include "uvm_macros.svh"
import uvm_pkg::*;
//////////////////////transaction class//////////////////////
class transaction extends uvm_sequence_item;
`...
- 13
1
vote
0
answers
347
views
Array slices are not supported for continuous assignment
I'm trying to index into a 2D array in Verilog like this:
`include "src/elementwise_multiplication.v"
module parallel_elementwise_multiplication_dynamic #(parameter N = 8, parameter M = 2) (
...
- 19
1
vote
1
answer
361
views
No .vcd file found error, but I have used the $dump code
I have been trying to open EPWave at EDA playground, and it always returns the error:
No *.vcd file found. EPWave will not open. Did you use
'$dumpfile("dump.vcd"); $dumpvars;'?
I have ...
- 13
1
vote
2
answers
295
views
Index-based Array Right Shifter using concatenation; Error: range is not allowed in prefix
I am trying to implement an array Right Shifter.
It accepts an array of integers, then right shifts everything to the right-side of specified index position, and inserts a specified integer value at ...
1
vote
1
answer
107
views
Why am I getting don't-care in the output of IIR filter?
module IIR_filter(xn, clk, rst_n, yn);
input signed [3:0]xn;
input clk,rst_n;
output reg signed [3:0]yn;
reg signed [3:0]y_1,y_2,x_1,x_2,x_3;
always @(*)begin
yn = xn - (x_1) + (x_2) +...
0
votes
1
answer
81
views
BDC to 7-segment decoder missing VCD file [duplicate]
When I run this code to EDAplayground, it will give me an error of:
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?
//Verilog ...
- 1
0
votes
1
answer
925
views
EDA Playground: No *.vcd file found. EPWave will not open
I am trying to run the following VHDL code for a digital clock, but I am encountering an error message and I am not sure how to fix it.
This is the link to my code in EDA Playground
library IEEE;
use ...
- 11
1
vote
1
answer
883
views
EDA playground ERROR VCP5294 "Undefined package uvm_pkg"
I'm trying to compile a small UVM verification environment in EDA playground.
I'm getting this error:
EDA playground ERROR VCP5294 "Undefined package uvm_pkg.
The code attached below:
import ...
- 11
0
votes
1
answer
428
views
(vcom-1339) Case statement choices cover only 6 out of 10 cases
Case statement choices cover only 6 out of 10 cases for my vending machine code I am getting this error after execution of my very long program in VHDL. However its said that When others => can be ...
1
vote
1
answer
2k
views
Warning: Only a single slice of data found. Did you specify valid 'From/To' times?
I've typed a design code and a testbench code for inverter circuit. The input is of 4 bits, and so is the output. I've tried to display the waveform using:
$dumpfile("dump.vcd");
$dumpvars(...
- 95
-1
votes
1
answer
421
views
VHDL Question with EDA playground - Illegal non-graphic Character
I am facing with problems with VHDL with EDA playground - Any solutions are welcomed.
design.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith....
- 13
3
votes
2
answers
1k
views
Using typedef with wire in SystemVerilog
When using typedef to declare a user-defined type, both these forms are accepted by EDA Playground:
typedef reg[4:0] reg5;
typedef logic[4:0] logic5;
However, if doing something similar based on wire ...
- 115
0
votes
2
answers
287
views
Why does this Verilog module show "invalid module item" on the 9th line?
I was learning about loops in Verilog and wanted to create a simple clock with time period of 20ns. I am getting the error below whenever I am trying to run the code in EDA Playground.
module Pulse(...
1
vote
2
answers
4k
views
Error by VCS tool on uvm_hdl_deposit usage on edaplayground
I am trying to execute code @ https://www.edaplayground.com/x/e2Pe.
The code seems to be error free. However, when trying to simulate with VCS tool, it is giving me below error:
UVM_ERROR: set: unable ...
- 11
-1
votes
2
answers
758
views
Virtual method 'write' not implemented in class
Hello I am getting the above error for the subscriber class I created as following:
The error seems in the write function of the class but I am not sure what I am missing in the function.
`...
- 33
1
vote
1
answer
8k
views
EDA Playground EPWave $dumpfile error: no vcd file found
I am trying to simulate my design in EDA Playground. I tested my design file and testbench file in my local computer using ModelSim (not from EDA), and it was successful. However, I tried to do the ...
- 171
0
votes
1
answer
2k
views
How to assign value to std_logic_vector in VHDL?
I am trying to assign value to OUTPUT std_logic_vector in the below code, but it gives me errors that
COMP96 ERROR COMP96_0143: "Object "OUTPUT" cannot be written." "design....
- 75
1
vote
1
answer
3k
views
Hello World testbench error: expecting an '=' or '<=' sign in an assignment [9.2(IEEE)]
I modified a "hello world" UVM testbench on EDA Playground to create hierarchy of UVM sequence. While creating object of base class sequence from the virtual task body of the child class, I ...
- 1,232
2
votes
1
answer
317
views
Verilog testbench error multiplex 4x1 using EDAPlayground
I'm doing a Multiplex 4x1 in Verilog using EDAPlayground, but I still get testbench errors, and I don't know why.
Here is one error:
ERROR VCP2000 "Syntax error. Unexpected token: and[_AND].&...
- 43
3
votes
1
answer
3k
views
Using Systemverilog to read then print binary file. First bytes read & print ok, trouble\w byte containing a 1 in the ms bit position encountered
The Systemverilog code below is a single file testbench which reads a binary file into a memory using $fread then prints the memory contents. The binary file is 16 bytes and a view of it is included ...
- 2,620
0
votes
1
answer
267
views
Errors in VHDL using WHEN ELSE
I'm new in VHDL and have simple errors.
Basically I have 4 binary inputs and 3 binary outputs.
The conditions are simple, if in all 4 inputs I have only one '1', output l3 receives '1' and the others ...
1
vote
1
answer
5k
views
EDA Playground $dumpfile: No *.vcd file found
I am having trouble getting some code to run in EDA Playground. I keep getting the message:
No *.vcd file found. EPWave will not open. Did you use
'$dumpfile("dump.vcd"); $dumpvars;'?
But, ...
user13442501
0
votes
1
answer
3k
views
dumping vcd files in Modelsim simulations
I am trying to dump a vcd file when simulating with modelsim, however, I don't get anything in my "dumpVCD.vcd" file. The syntax I am usingin .do file is as follows:
vcd file dumpVCD.vcd
vcd add -r /...
- 195
2
votes
1
answer
2k
views
EDAplayground error: Execution interrupted or reached maximum runtime [duplicate]
It has some error in my code, but I can't find anything wrong with my code. EDA Playground says:
Execution interrupted or reached maximum runtime.
Here is my code:
forever #5 clk = ~clk;
- 31
0
votes
1
answer
214
views
Merging events doesn't trigger both events
I'm trying to run some code from chipverify website in Modelsim and my output is different than on website. Example from website is about event merging.
module tb;
// Create event variables
event ...
- 5
1
vote
2
answers
2k
views
Verilog race with clock divider using flops
I made a basic example on eda playground of the issue I got.
Let s say I have two clocks 1x and 2x. 2x is divided from 1x using flop divider.
I have two registers a and b. a is clocked on 1x, b is ...
- 160
0
votes
1
answer
513
views
Signals not going forward from initial state in Verilog test bench
I am working with a system of two d_flipflops (DFFs) connected to each other (with output,q, of first DFF connected to input,d, of second flipflops. I created sub-modules of DFFs and embedded them ...
- 5
1
vote
0
answers
5k
views
Facing errors while running VHDL code using EDA playground
I'm trying to run the following VHDL code using EDA playground as no VHDL simulator is installed on my Laptop. The upper part is the source code and lower part is the testbench. However, getting some ...
0
votes
1
answer
2k
views
EDA playground file compile order
If there are number of files in EDA playground (SV/UVM), including the the packages, etc., how does EDA playground take care of compile order? Is the package file compiled first?
If it doesn't care ...
- 17
0
votes
2
answers
5k
views
Execution interrupted or reached maximum run time in edaplayground
Execution interrupted or reached maximum runtime.
Here is the link for my code:
http://www.edaplayground.com/x/CX8
I am trying to swap numbers in this design.
1
vote
1
answer
3k
views
DFF in verilog with a delay
I'm trying to implement the nand2tetris project in verilog and am hitting a wall using icarus verilog. In the book they implement the DFF as so, q(t) = d(t-1). The output at the current time is the ...
- 4,403
4
votes
1
answer
3k
views
How to compile and run a verilog program which calls C function?
I am not trying to use a DPI call, but a simple Verilog program which internally uses its PLI to call a function written in C language. I don't know about static linking. I am using edaplayground.
...
- 524
3
votes
1
answer
318
views
Issue with reading bus signal. Compare to my Modelsim DE 10.2c and 10.4. EDAplayground Modelsim 10.1d has different result
Hi any SystemVerilog experts with Mentor Graphic Modelsim Tool.
I am writing a monitor task to process a simple PCI single word write/read bus event. Somehow EDAplayground Altera Modelsim 10.1d ...
- 53
2
votes
1
answer
1k
views
Clock waveform does not show in EDAplayground
When trying to get the Clock waveform to display in EDA Playground I get the error
Execution interrupted or reached maximum runtime.
How do I get the wave form to show?
Code on EDA Playground:
...
- 31
2
votes
1
answer
166
views
Unable to display the simulation with EDAPlayground compiler
I have tried the following code from myHDL manual on EDAPlayground.com, but it didn't print anything out for me. Can anyone show me why and how to solve this?
My configuration on the site is outlined ...
- 33