2,824 questions
2
votes
2
answers
82
views
Proper way of resetting a FSM
I usually work with Xilinx FPGA boards. Based on the documentation I've reviewed and the research I've done, I try to avoid using a global reset signal in my designs as much as possible. However, let'...
- 21
-1
votes
1
answer
122
views
Difference between signal and variable in VHDL (FPGA hardware perspective, not just simulation)
I understand the usual textbook difference between signal and variable in VHDL:
variable := updates immediately inside a process
signal <= updates after a delta cycle
variables are local, ...
0
votes
0
answers
47
views
AXI DMA Linux Driver on ZynqMP
I have a ZynqMP board with 4GB of PS RAM and 2GB of PL RAM. I have to write stream data to PL RAM using the AXI DMA s2mm channel and transmit it through 1G Ethernet. I've done this in a bare metal ...
2
votes
1
answer
86
views
Why is my simple ARM7 data memory on Verilog failing tests?
I'm implementing a simple ARM7 in Verilog and am currently in the process of creating a simple data memory. I've come up with something like this:
// very simple sdata implementation with 1mb~ memory
...
- 301
0
votes
0
answers
34
views
How to resolve license check error when using rfnoc_image_builder to build fpga image
The build failed at 'Adding block description from license_check.yml' as shown below in bold
# Snapshot of build
blackvoid@blackvoid:~$ rfnoc_image_builder -F $UHD_FPGA_DIR -I $RFNOC_OOT -y $RFNOC_OOT/...
0
votes
0
answers
68
views
How to setup approriate configs for single-core rocket-chip Gemmini Accelerator?
I'm buiding a single-core rocket chip, which use an Gemmini interface to do systollic array, and I use board Arty-Z7 to run demo on FPGA. My problem here is I don't know how to choose a suitable ...
- 1
0
votes
0
answers
49
views
FTDI Communication Problem with Pylibftdi on a Windows Machine
I have a Digilent Nexys Video Artix-7 FPGA development board. This board has two Micro USB ports. One is used for UART-USB communication, and the other one for uploading bitstreams(as a JTAG). I ...
0
votes
0
answers
83
views
programming DDR to produces samples for RFSOC4x2 question
This is programming FPGA question so its both programming in C and hardware.Hope its suitable for this forum and If not I'll be glad to get a more suitable place to post this question.
I am building a ...
- 101
-1
votes
1
answer
85
views
In a System Verilog FSM can a repetitive State be converted to a Task?
I'm writing an FPGA state machine in System Verilog to read bytes from a SPI port and parse them into commands to the FPGA. The "RXSPIBITS" state is used to read SPI bytes by multiple other ...
- 9
0
votes
0
answers
60
views
How to fix State <name> contains multiple transitions, but more than one transition equation are TRUE when <text> in Quartus?
I'm trying to develop a Elevator FSM machine in quartus in order to get his equivalent to HDL code. The FSM is this:
But when I set the Input, transitions and output in "State Machine Wizard&...
- 71
1
vote
1
answer
99
views
Should UVM testbench work with pre-synthesis or post-synthesis FPGA code? [closed]
I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow.
Should I develop my ...
- 139
0
votes
0
answers
71
views
Why does module instantiation affect output reg value in vivado? [duplicate]
The instantiation module as below:
module second_module(
input [7:0] d,
output reg [7:0] q
);
initial
q <= ~d;
endmodule
The top module as below:
module top_module(
input [7:0] ...
- 2,513
0
votes
1
answer
88
views
`$strobe` and `$display` output different result for the same target
Refer to this question,I write a similar case.
module n;
reg [1:0]a, b;
initial begin
a=1;
a<=a+1;
$strobe("strobe",a);
$display("display",a);
end
endmodule
The ...
- 2,513
-1
votes
1
answer
110
views
How to run iterations through a module instance without using generate in Verilog
I'm a complete beginner when it comes to Verilog.
I have a block ROM which is as follows:
module CDbram_2_0_32 (clk, en, addr, dout);
input clk;
input en;
input [9:0] addr;
output [9:0] dout [0:37];
(...
6
votes
1
answer
119
views
Deallocating after returning line using std.textio ieee library
A known problem in VHDL is that using parts of a return statement (e.g to_string(slv(i))'length) will generate a warning/error on compile. To work around an unknown string length, I tried using the ...
- 131
2
votes
2
answers
221
views
Efficient 16-bit std_logic_vector comparator in VHDL
I'm working on a VHDL project where I need to implement a comparator between two 16-bit std_logic_vector signals, a and b. The goal is to check if a is greater than, less than, or equal to b.
The ...
- 21
2
votes
0
answers
86
views
Quartus Prime flexible RAM ip component
In Quartus II it was possible to make a flexible RAM component with a little "generic" modification to a SINGLE file generated by MegaWizzard manager. So it was so easy and fast to add ...
0
votes
0
answers
121
views
Verilog I2C Master Communication with SSD1306 OLED Not Working
I'm working on coding an I2C Master module in Verilog using the Zybo Z7-10 board.
My goal is to control the SSD1306 OLED driver via I2C communication.
As far as I can tell, my timing diagram fully ...
-1
votes
1
answer
177
views
How to use `get_nets` to find `wire` in Vivado when get Vivado 12-1023 warning?
Verilog script as below:
`timescale 1ns/1ps
module Save_Mult_Df(A);
input A;
wire C;
assign C=A;
endmodule
module test();
reg A;
wire C;//should wire be added to testbench?
initial
A= 2'b10;
...
- 2,513
0
votes
1
answer
127
views
DE1-SOC 5CSEMA5F31 isn't detected in Quartus Program Device
I'm having trouble programming my DE1-SoC from the Quartus Programmer. The board is powered and connected correctly and I've managed to find and program it before, multiple times, but even then ...
- 71
3
votes
1
answer
122
views
Verilog full adder
This is the Verilog question. I have written the code according to the image, but I'm getting mismatch in the output, can I get some assistance?
module add1 ( input a, input b, input cin, output ...
- 73
0
votes
1
answer
91
views
For some reason, when allocating memory from user space linux, I have a problem with the write response in AXE Memory Mapped to PCI Express module
I have a PC as a root complex and Xilinx fpga device as an end point that writes via PCI Express to root complex RAM using DMA and a linux driver to it. I have a problem that I can't solve in any way. ...
- 1
0
votes
0
answers
54
views
m_axis_result_tvalid is not asserting during floating point operation
I'm trying to do some operations in a Xilinx FPGA. Here is my code. When i simulate the code, the error validation signal does not assert. i need the signal to allow the next step of operations to ...
- 11
0
votes
1
answer
1k
views
Vivado 2024.1 – Warning: [Synth 8-7080] Parallel synthesis criteria is not met – what does it mean and how to resolve it?
I'm using Vivado 2024.1 with full-project synthesis (not out-of-context), and I’m getting this warning during synthesis:
[Synth 8-7080] Parallel synthesis criteria is not met
The design builds and ...
- 6,771
3
votes
2
answers
73
views
ATF16V8, is it possible to use OE value
Good day to everyone.
I suppose the answer to my question will be no, but maybe I misunderstood something.
I need to make an 8-bit flip-flop, with a preset (constant) on the RESET signal.
It would ...
- 63
2
votes
0
answers
111
views
Shared memory between RISCV vm (using Qemu) and host
I can't set correctly shared memory for Qemu RISCV emulation.
My intention is to create a portion of shared memory between Qemu RISCV emulator and the host server. I need this because my intention ...
- 21
2
votes
1
answer
114
views
Is it okay to use level-triggered registers on an FPGA? [closed]
I'm trying to make a single-cycle processor and I was planning on doing something like the following:
Clock rising edge: Opcode is latched onto output of block memory (this must be on a rising edge), ...
1
vote
1
answer
93
views
Winsocket UDP : works only when wireshark launched
I have FPGA device which is waiting for UDP packet "FFFF" on port 1000, then answers also with UDP "FFFF".
This code works fine, I see incoming "FFFF" packets on my JTAG, ...
- 13
2
votes
1
answer
100
views
Is it possible to add external SRAM on a FPGA card
When considering deploying a deep learning model on an FPGA acceleration card (such as an AMD Alveo U50), the onboard SRAM may be insufficient, and its bandwidth is significantly higher than that of ...
- 133
1
vote
0
answers
157
views
srsUE on FPGA not connecting to srsRAN
I'm running srsUE on FPGA, buildroot with 2 CPUs and 1G memory. srsRAN is running on my laptop, ubuntu 22. I use dockerized version of 5gc.
srsUE and srsRAN connected through ZMQ and on a local ...
- 35
0
votes
1
answer
346
views
What's the difference between a constant and an inline constant in Vivado?
I'm currently working on a simple project on an FPGA and wanted to set an enable-input to 1. Now when using the built in IPs for a constant, two components show up. One is "Constant" and the ...
- 13
1
vote
1
answer
70
views
Xilinx 7 overwrite LUT contents after flashing
I want to be able to change device behavior during work
Can I overwrite INIT values of LUT within FPGA work process?
I've seen, that I can use it as LUTRAM, but I also want to be able to shift data ...
- 181
-3
votes
1
answer
119
views
Using Finite State Machine model to design LCD1602 driver in VHDL [closed]
I am designing a driver of the classic LCD1602 module by VHDL. There are many good examples on the web. But when I tried to write it in my own way, I just can't make it work. Here is my code.
library ...
- 21
0
votes
0
answers
42
views
2 Stage Synchronizer confusion
In this picture, Ds goes metastable during the second rising edge of CLK-B because Din changed values during its aperture time at the first rising edge of CLK-B. However, Ds can go metastable during ...
4
votes
2
answers
147
views
Issue with driving an LED matrix using an FPGA (Verilog)
I am trying to run an LED matrix using an FPGA. The specifics are a TinyFPGA BX, wired into this board (driver chip datasheet), connected to this screen. Before this, I managed to drive this matrix ...
- 43
0
votes
2
answers
102
views
SystemVerilog intermediate top output signal
I am wondering which SystemVerilog coding fits better for ASIC/FPGA Synthesis/linting. I mean for simulation/synthesis/... purpose if it makes any difference and if a coding style is preferred, for ...
- 35
0
votes
1
answer
257
views
TCL Script for Including Date and Time in Top Module of Design Sources in Vivado
I’m trying to write a TCL script in Vivado 2021.2 that dynamically includes the current date and time in my top module by fetching the name and path of the top module.
The following TCL command works ...
- 11
1
vote
1
answer
134
views
LED Sequence on Basys3 with Verilog
I need this for a school project. The professor wants an LED sequence if the x is zero (which would mean the sw is 0) that would go:
0000000000000001
0000000000000010
0000000000000100
0000000000001000
...
- 51
1
vote
1
answer
58
views
Is it a bad practice to reset a variable in one model using a variable from another model?
I'm building a vending machine. I want the pay sum to maintain its value until the candy is out or canceled.
To simplify, is it ok to build a reset this way:
module m1(
input clk,
input m2_reset,
...
0
votes
0
answers
86
views
Verilog Daisy-Chained Ripple Counter in actual FPGA
I am writing cores for old arcade games in Verilog. Firstly I create the simulation, based off the arcade schematics and then proceed to FPGA. I have a problem of metastability when reproducing the ...
1
vote
1
answer
67
views
Binary - BCD convertor works in sim, but does not work on FPGA
I defined a binary to BCD converter to use on a Basys 3 development board. In simulation, the results are as expected, and it follows the timing exactly.
I included the BCD converter in a top module, ...
- 35
0
votes
1
answer
64
views
NEC Infrared Transmission Protocol in C lanc on Xilinx [closed]
I need to capture and decode an infrared signal (with NEC infrared protocol) using a GPIO pin on a Xilinx FPGA and show the content of the signal on the console. I receive the signal on the address
...
- 63
0
votes
1
answer
92
views
My SDRAM can keep data valid forever without refreshing, how can this be possible?
I designed a simple SDRAM driving module with Verilog HDL. The module defines a simple finite state machine. It performs initialization of the SDRAM (Winbond's W9825G6KH 4M * 4Banks * 16bits) in the ...
0
votes
1
answer
113
views
Vivado 2018.3 generate bitstream consume a lot of time
I am using Vivado 2018.3(on Ubuntu 22.04) and my project is about pcie xdma,not very big project.
The syn and implementation part takes about 5 minutes , and it report time failed.
But I want to ...
- 21
0
votes
1
answer
92
views
Vitis HLS change of datatype makes variable unused
I'm trying to implement a signal processing algorithm in Vitis HLS.
For this, I read in a few variables via AXI Stream and AXI Lite.
Simulation and synthesis did already work with the complete project....
- 41
0
votes
1
answer
161
views
Fifo initialization and data transmission in Vitis
I have a relatively simple design, and I’ve attached the diagram below. In short, it’s meant to perform a loop where one core sends data to the FIFO, and another core initializes the DMA and waits to ...
- 313
-2
votes
1
answer
62
views
Inverting pin value in physical constraints (Gowin EDA)
I've recently bought a Tang Mega 138k Pro fpga board. it contains some peripherals (switches, led, ...) that are active low. Is there any way to invert the pin in physical constraints file so i don't ...
2
votes
1
answer
1k
views
Vivado design checkpoint
I am quite new to this.
Hopping into an existing project, which had both bin and dcp files commited in to git. These have constant conflicts, which makes sense to me. As generated files, my take is ...
- 42.4k
0
votes
1
answer
269
views
Yosys/nextpnr timing report for Lattice ECP5 FPGA?
I have a ECP5 project that I build using the commands below. How can I get a timing report for it (e.g. the max clock speed for that design)?
yosys -p "synth_ecp5 -top Test -json hardware.json&...
- 125
-1
votes
1
answer
70
views
Assigning the same register multiple times in the same always block but with different conditions
I have a question.
so I know that in this code:
reg a;
always @(posedge clk) begin
if (enable1) begin
a <= 0;
end
if (enable2) begin
a <= 1;
end
end
enable2 gets ...