2,824 questions
-4
votes
1
answer
193
views
High Level Synthesis Stream splitting inside a function (FPGA openCV acceleration)
i try to split a HLS stream which is incoming from the interface. This stream contains a data stream and a user stream with control signals (startFrame, stopFrame, startLine, etc).
I want to use an xf:...
- 1
-2
votes
1
answer
154
views
Mismatch between behavioral simulation and post-synthesis functional simulation in vivado
I am writing a VHDL module to convert an incoming stream via axi stream (tdata, tvalid, tready and tlast) with tdata's with 8 bits such that the fist 4 bytes are registered in the output port A of 32 ...
- 57
-1
votes
1
answer
796
views
how to force block ram instead of LUT in VHDL?
xc7s25csga225-1 FPGA
Vivado v2023.2.2 (64-bit)
VHDL
i keep getting the error:
[DRC UTLZ-1] Resource utilization: F7 Muxes over-utilized in Top Level Design (This design requires more F7 Muxes cells ...
1
vote
1
answer
332
views
Ambigious clock in event control
I want to generate a slow clock from input clock which is clk_in, but it shows the following error:
ambigious clock in event control
module clk_div_h(rst, clk_in, clk_div);
input rst, clk_in;
...
- 11
-1
votes
1
answer
100
views
Counter output not synchronized to clk in vhdl in real fpga
I am trying to figure out why there is instable output of simple counter. I am using Sipeed Tang Primer 20k development board based on GW2A-LV18PG256C8/I7 FPGA. I created simple project, which uses ...
- 9
-1
votes
1
answer
106
views
modelsim can't find object (vish-4014) and i it doesn't show any wave so that can i add it to scope
this is my code for a fun Fire extinguishing system in a 50 unit apartment.this is fire_detection_system.v:
module fire_detection_system (
input wire clk, // Clock signal
input wire reset, // ...
- 1
1
vote
1
answer
162
views
how can i find message window in Quartus
There are no messages window below the code blocks
I'm using Quartus eda tool for fpga jobs with verilog HDL.
For compiling, i need message window to know errors in my code blocks.
But i can't find ...
- 11
1
vote
1
answer
503
views
UHD 4.7 FPGA image creation
I have an Ettus E310, and I used UHD 3.14 to create a custom FPGA image containing the Window, FFT, and LogPwr RFNoC blocks. In that version, I used uhd_image_builder.py like so:
source ~/rfnoc/src/...
0
votes
0
answers
109
views
Linux Clock source from FPGA
I'm trying to get the Linux kernel (and system as a whole) to sync to a monotonically incrementing clock from a FPGA register in memory. The clock is 64-bits wide and divided into two 32-bit sections: ...
0
votes
0
answers
106
views
Data Missing in FIFO stream after DMA transfer
We have a DMA design with FIFO stream input.
We let FIFO accumulate the entirety of data stream i.e., 0x8001 depth and width is 32 bit.
Then we cut off the Input stream to FIFO since it is external.
...
- 21
0
votes
1
answer
80
views
mscorlib Error Occurs when Building Simulink Model using HDL Coder Workflow Advisor
I have a simple Simulink model that I want to build into FPGA code compatible with NI FPGA targets. I have installed the HDL Coder and the HDL Coder Support Package for NI FPGA Targets.
When I try ...
0
votes
1
answer
1k
views
When should I use a function over a procedure? [closed]
I've been trying to understand when to use a Function and when to use a Procedure in VHDL. From my understanding both are Synthesizable. You use a Function when you have 1 return value and a Procedure ...
- 13
0
votes
1
answer
142
views
What is wrong with the array constant declaration in my VHDL code?
I am a digital technology student trying to learn VHDL.
I wrote this testbench code for 4 bit bcd adder to 7 segment display
I have tried all the possibilities i and chat GPT could think of but the ...
-1
votes
1
answer
150
views
assign SD card pins used by HPS for FPGA DE1-soc
I am following a tutorial and making some changes to it. thi sproject uses Nios2 and the goal is to use the SD card slot from the DE1-soc board and read a bmp image file from the sd card and send it ...
- 1
0
votes
1
answer
245
views
How to combine a FSM with BRAM?
My project is as follows: I want to save the pixel values coming via UART to BRAM first, then pass them through an image processing filter, and send them back via UART. Currently, I want this filter ...
- 1
-2
votes
2
answers
225
views
How to write firmware in vivado?
I’m a logic designer and never written firmware before. On top of that, I have been assigned with task to develop firmware in vivado. I did spend some time learning tool but it’s seems like a ...
- 21
0
votes
2
answers
327
views
SystemVerilog unconnected port
I am wondering if there is any difference between these two connections, I know the first case can accept default value, but my question is rather from a netlist point of view :
Unconnected port
...
- 35
0
votes
1
answer
628
views
VHDL Hierarchical Reference within/to Generate Statement(s)
I'm looking for some help with hierarchical reference when using generate statements. Apologies, I am short on time and haven't yet been able to make a MCVE for this. I've scoured many posts, but so ...
- 320
0
votes
1
answer
178
views
Is it possible to tie ports high always high outside of top module?
I'm programming the Xilinx BASYS 3, Artix 7 board. It has 7-seg display with 4 anode ports. When I ignore them in code they are low causing the 7-seg to be on. Is there a way to make tie them high in ...
- 73
1
vote
1
answer
2k
views
Vivado Error: [DRC MDRV-1] Multiple Driver Nets
I am running into an error on Vivado. I am trying to run implementation to program my Basys board, but I am running into the following error:
[DRC MDRV-1] Multiple Driver Nets: Net ScrlFSM/RLC2B/DER1/...
-3
votes
1
answer
135
views
How to add SD driver on KC-705 from Xilinx in Vivado BD
When I trying to add ip core for sd card in vivado block design, it write errors while generating bitstream.
Errors is "Unspecified I/O Standard" and "Unconstrained Logical Port" ...
- 1
-2
votes
1
answer
96
views
Cannot get modules to connect properly using wire connections through a finite state machine (FSM)
My project is essentially a song player that doesn't actually output sound but instead outputs the note (i.e. A, G, D, B) on the Basys 3 FPGA 7-segment display with the specified timing using flags.
I'...
1
vote
2
answers
132
views
Assign a Verilog output state from that of a register
I am new to Verilog. I keep getting this error in vivado programming a basys3 board: Vivado Error
here is my Verilog code, It is a simple state machine that changes state on each clock cycle. below ...
- 11
1
vote
1
answer
154
views
PCIe BAR access
I have a FPGA card plugged in to a host memory over PCIe. I want my host to access 2GB of DDR memory on card. Does that mean I'll have to request for a BAR size of 2GB ?
My understanding is that, if I ...
- 43
-1
votes
1
answer
418
views
uart in vhdl send a string
I am learning vhdl and fpga, I have a digilent board Nexys 4. I am trying to send via UART a string. I have been sucessful in sending a character every time a button is clicked on the board.
Now I ...
- 507
0
votes
1
answer
477
views
IO placement is infeasible error in Vivado
I'm getting an error while running implementation in Vivado. This is my top level module:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Single Cycle ARM Processor
entity Processor is
port (
...
- 308
0
votes
1
answer
369
views
Why RTOS is needed for FPGA based real-time embedded system?
I am new to real time embedded systems. As I learned RTOS is used for task scheduling. If the system is simple, interrupts can used apart from using RTOS. I wonder if I use FPGA for my real time ...
0
votes
1
answer
139
views
Padding zeros with std_logic_vector results in Implementation Error
I'm encountering an issue with Vivado where zero-padding in my VHDL code is not being preserved in the elaborated design and results in Implementation Error. Here's a brief overview of the problem:
I ...
- 11
0
votes
1
answer
148
views
How to write into 12 addresses at the same cycle in vivado and still be recognized as BRAM
This is the original code,It is synthesized as a BRAM
module RAM_IMAGINARY (clk, we, en, addr, di, dout);
input clk;
input we;
input en;
input [7:0] addr;
input [15:0] di;
output [15:0] dout;
logic [...
1
vote
1
answer
130
views
Verilog module always going to default case when assigning value to input
I'm just starting to use Verilog. One of my first projects has been a module that controls 4 7-segment displays with a 16-bit input. My BCDtoSSeg module is the following:
module BCDtoSSeg (BCD, SSeg);
...
- 37
0
votes
1
answer
225
views
Failed to use memory bits in fpga
This is a code for a 2 port data memory. When I compile it on quartus, number of memory bits are zero and is implemented as logic elements and doesn't infere a ram.
How to solve that?
module ...
- 11
0
votes
1
answer
199
views
Can SYSCLK be included in FPGA Xilinx vivado testbenches?
I'm doing a fairly simple design. I have the VC707 FPGA Evaluation Board and from the SYSCLK(P/N) I'm generating a single-ended clock for the rest of the board.
// Differential to single ended buffer ...
- 25
0
votes
1
answer
175
views
Are FPGA GPIOs capable enough to read bits at a high rate (26Mbps)? If not, what is a possible way? [closed]
I had two systems, let's say, system A and system B, so system A generates bits at the rate of 26Mbps from a physical pin, I need to capture/read all the data with system B which is ZC706 FPGA/any ...
0
votes
2
answers
72
views
not showing the proper output
These modules and testbench in SystemVerilog are used to multiply a two-bit number by 3 and give a four-bit result; however, when i simulate it, it shows X as an output. i checked my modules but ...
-1
votes
1
answer
281
views
Determine if a module in SystemVerilog is synthesizable
I am implementing a max-pooling module on FPGA using SystemVerilog. The length of each word is 64 bits, a grid of 28 by 28 words is input data (which is an image 28x28 pixels). The filter size is 2 by ...
- 301
1
vote
1
answer
660
views
Verilog: mapping an memory array
I'm trying to make a memory in system verilog and it can be synthesised only when I want to write to the memory directly.
Here is a code that DOES work:
module top (
input logic clk_i,
...
- 111
0
votes
2
answers
89
views
Is it possible to restrict UDP packets being sent to an FPGA to a single host?
I'm trying to send data from a Qt application on a Windows 11 PC to an Arty A7-100T equipped with the Xilinx TEMAC IP Core.
Currently the Qt app just consists of a start/stop toggle button that, when ...
- 51
0
votes
2
answers
300
views
How to initialize coefficients of a large digital filter in Verilog?
I am trying to make a synthesizable filter in verilog. I have the fixed-point filter coefficients in a text file. I am looking for an elegant and scalable way to pass on these filter coefficients. The ...
- 200
-1
votes
1
answer
198
views
Should my PC recognize my Arty A7-100T FPGA?
I'm developing a data acquisition program that will send data collected by an FPGA back to a PC over ethernet for visualization. When the Arty is powered and plugged into the PC via ethernet though, ...
- 51
0
votes
1
answer
302
views
VHDL: using rising_edge with normal signals
If we generate a "clock_enable" signal just as suggested in this accepted answer:
Is the use of rising_edge on non-clock signal bad practice? Are there alternatives?
Like:
signal mySignal_d :...
- 501
1
vote
1
answer
179
views
How many additions operation can be performed instead of single multiplication in FPGA?
How many addition operations can be performed instead of a single multiplication on FPGA? In terms of used resources - as an example - energy and logic area cost. I would like to know it for multiple ...
- 43
0
votes
1
answer
122
views
FPGA Fancy flowing light, digital tube display?
Here is the Question:
The input clock is the clock generated by the onboard 50MHz crystal oscillator, and after passing through a frequency divider, a 1Hz clock is obtained. The flowing light is ...
- 97
1
vote
1
answer
58
views
What is "strictly control signal" and Why is its input unconstrained?
This is from book "STA for nanometer design"
This section describes the constraints for the input paths. The
important point to note here is that STA cannot check any timing on a
path that ...
- 115
3
votes
2
answers
197
views
How do I represent large delays in Verilog?
I want to use a delay of 5s in my Verilog testbench. However, the time scaling is 1ns/1ps. I do not want to change this scaling since it effects my clock.
But, how can I write a delay of 5s which is ...
-3
votes
1
answer
81
views
Is it possible to fill an array with a single operation?
In C, you can do this:
int a[5] = {1, 2, 3, 4, 5};
On VHDL, I need to do about the same thing in a function. Now it looks like this:
type rom_type is array (0 to 1) of std_logic_vector(1 downto 0);
...
0
votes
1
answer
144
views
Verilog Perceptron pipelined module output is one clock behind compared to given testbench
I designed a single layer perceptron for a lab I need to finish. It is working perfectly as expected, and I am receiving the expected output compared to a testbench given to us. The only issue is that ...
- 31
0
votes
1
answer
250
views
oss-cad-suite not installed error when running "apio verify"
I'm currently running Windows 11 with Python 3.7.9 and trying to get apio version 0.8.3 to work. When I try to run apio verify in a valid folder with an apio.ini file (from apio examples -d icestick\...
-2
votes
1
answer
500
views
Why does running Synthesis take the same amount of time every time with Quartus, Vivado and Libero?
With all FPGA tools I have used so far: Intel Quartus Prime, Xilinx Vivado, Microsemi Libero SoC, it always takes the same amount of time whenever I run synthesis. What I would expect is that the ...
- 708
0
votes
0
answers
123
views
RISC-V softcore GPIO (memory mapped) sends the first value and fails later
I have a RISC-V softcore based SoC (PICO-SoC) and I have implemented memory (32'h 00000090) mapped output port to send a set of values. The set up is running on PYNQ FPGA board. The softcore provides ...
- 29
1
vote
1
answer
1k
views
How to remove/unload a device tree overlay to program FPGA multiple times?
I can program the FPGA part of an Altera/Intel Cyclone V SoC FPGA with a firmware, from Linux on the HPS (ARM core in the SoC FPGA), using Buildroot.
I'm using a device tree overlay to write a raw ...
- 507