2,824 questions
-1
votes
3
answers
270
views
Blocking the clock signal
Let's say I need to find out that the BLOCK signal came earlier than the 5 clk signal. These signals are asynchronous to each other, so I can't use the classic construction as shown below.
always(...
- 13
0
votes
1
answer
117
views
Error (10453): VHDL error at <> right bound (0) of slice must belong to range (54 downto 5) of corresponding object
I am making an Avalon memory mapped component.
I wish to send the data of the registers directly to another VHDL entity. But doing this gives me the following error.
The error is when I try to add the ...
0
votes
1
answer
122
views
How Can I Use Components in FPGA?
I want to use Port Maps inside of the if cases (in and gate case), but I could not use it. What is the problem? I am really new in FPGA coding. Can you help me with the code side? When I use it ...
user22269571
0
votes
1
answer
188
views
how to automatically remove the redundant .coe file in vivado by automating tcl script?
i have been assigned a project where there is a redundant /missing .coe file under coefficients file directory which no longer required in the given project of vivado. project will open in vivado ...
-1
votes
1
answer
689
views
Type conversion issue with 'std_ulogic' - seeking guidance
I'm working on a VHDL project involving button presses, and I've encountered an issue that I can't seem to crack. In the following line of my code:
button_counts(i) <= std_logic_vector(unsigned(...
0
votes
1
answer
372
views
FPGA/VHDL Trying to impelement a shared memory between my Basys 3 FPGA Board and a MicroBlaze Softprocessor
I am very beginner at FPGA technologies and VHDL coding. I have a Basys 3 FPGA development board which has a Artix-7 XC7A35T-1CPG236C FPGA on it. What im trying to achieve is to create a MicroBlaze ...
2
votes
1
answer
684
views
Verilog state machine state/next_state style
I'm a Verilog beginner, and I'm trying to learn about the best ways to implement FSMs on the common FPGA platforms.
I have seen a number of papers (e.g., this one) that encourage a state/next_state ...
- 343
6
votes
0
answers
1k
views
Is there a way to have variable sized int and unsigned integer types in Rust?
In Rust, standard integer type are sized 8, 16, 32, 64, 128 bits.
But is it possible to manipulate integer types with a non-standard size like u24, i7, ... ?
These non-standard sizes can be useful ...
- 3,901
1
vote
1
answer
505
views
Produce sine lookup table based on the frequency
Trying to generate sine wave by using LUT. But, the LUT is calculated within the VHDL code as can be seen below. I do know that in VHDL it is not possible to use real. But couldnt figure out how to ...
- 101
-1
votes
1
answer
462
views
what is the actual and exact meaning of memory mapped terms used in context of register-interfaces in fpga design?
So many times, I have heard these terms in the FPGA design process, and to my knowledge, which I gather from a Google search, it's like some data is going to be transmitted from the core to memory.
...
1
vote
0
answers
255
views
Assigning 16 bit to 4 bit
I have this binary to bcd code. In the end I get 4 4bit bcd numbers. Basically I can say these are hex numbers.
module bin2bcd(
input [13:0] bin,
output reg [15:0] bcd );
integer i;
...
- 23
1
vote
1
answer
120
views
How can I enable data transfer through physical contact in FPGAs?
Using FPGAs, I am trying to bring at least some data to physical contact, but nothing comes to contact from the word at all. I use Xlinix.
Here's what the code looks like:
the main module that ...
- 25
-1
votes
1
answer
180
views
Fibonacci LFSR using the Altera Megafunction LPM_SHIFTREG - how to initialise? [VHDL]
I am having a frustrating time designing a linear feedback shift register where there is a need to use Altera's LPM's, in this case the LPM_SHIFTREG. This must be used as I have an assignment and exam ...
- 21
2
votes
1
answer
177
views
In FPGA, why counter with full adder raw implementation have better clock performance than infered addition '+'?
I'm testing counter and addition performances on ICE40 and Gatemate FPGAs.
I wrote counter in two differents way :
NaturalCounter using the operator '+' of chisel (view source):
// Natural counter ...
- 3,901
-2
votes
1
answer
139
views
Using the same entity to process data of different types - are the new VHDL 2008 features usable for that?
Many times I created VHDL blocks that may handle data of different types.
One example is a heap stream data sorter - https://opencores.org/projects/heap_sorter , another one is the data concentrator ...
- 850
0
votes
1
answer
1k
views
Enabling FPGA manager causes device tree related compilation error in Petalinux 2023.2 targeting Versal arch
The compilation of my PetaLinux image with 2023.2 version of the tool is crashing at the compilation of the device tree when trying to enable the FPGA Manager for a Versal target.
I am currently ...
- 1
1
vote
1
answer
97
views
is it okay to assign 1 bit reg data type element to 4 bit reg element?
i am trying to implement a rtl code where i am giving 1 bit reg data type to an 4 bit reg data type under always block.
lets say X & Y are two reg data type.where X is 4 bit reg data type and Y ...
0
votes
1
answer
126
views
SymbiYosys cover mode fails on checks that aren't covers
I am learning formal verification using PSL and VHDL with SymbiYosys.
I have the following test in Formal.psl:
vunit f_top_asm_verify(TopAssembly(Rtl))
{
default clock is rising_edge(i_clk);
...
- 49
0
votes
0
answers
38
views
FPGA Parallel output timing to satisfy input timing
Let's say a FPGA reads flip-flop D and outputs Q on the second rising edge of a CLK (figeure1). How can this satisfy the input setup time [TpdSU] of another device (figure2)?
Do they generally not use ...
- 11
1
vote
1
answer
187
views
'case item is unreachable' in Vivado synthesis process
`timescale 1ns/1ps
module lcd_control (
input clk,
input reset,
input prod1,
input prod2,
input prod3,
input prod4,
input disp_up,
input disp_down,
input confirm,
...
- 15
0
votes
0
answers
129
views
Verilog FPGA poor placement for routing between IO pin and BUFG error?
I've been encountering this error every time I have tried to run implementation of my modules on Verilog. I've looked into previous error flags related to this but the solutions aren't really working. ...
- 29
1
vote
1
answer
94
views
FPGA loads same bit file but the performance is different at different switch on times
Hardware design has 3 PCB's (each with 1 FPGA) connected through mother board. Communication between FPGAs is through GPIOs. Individually each FPGA code is taken care that there are no timing errors ...
- 11
0
votes
1
answer
246
views
expression has 16 elements; expected 17 elements
Vivado keeps notifying me about this issue of a mismatch between the two values at address <= address & std_logic_vector(to_unsigned(1, 1)), but I've checked and I shouldn't have an off-by-one ...
- 15
-1
votes
1
answer
145
views
I am trying to declare a Package to add 2 4-bit STD_LOGIC_VECTOR and return a 4-bit STD_LOGIC_VECTOR Result and 1-bit Carry
I an using Xilinx ISE Tool for it.
STEPS FOLLOWED:-
Created a Project in Xilinx ISE.
Added VHDL Package as a Source.
Wrote Code to declare the Package to add two 4-bit STD_LOGIC_VECTORs and return a ...
- 11
1
vote
1
answer
460
views
Analyzing synchronizer MTBF in Quartus
I have a message from Quartus that it found synchronizer chains, but is unable to perform MTBF analysis on them. Yet, nothing is really explained in the manuals except how to recognize synchronizers ...
- 22.7k
2
votes
0
answers
157
views
Troubleshooting Xilinx IP Core CPRI Link Between Master and Slave
I am currently facing a technical issue with my Xilinx project involving the CPRI link between the master and slave devices. Here's a breakdown of the problem:
In a single test loopback setup, both ...
0
votes
2
answers
3k
views
How to write data into bram and read data from bram?
I am trying to understand how writing and reading take place in BRAM memory under certain controlling situations. Please tell me if there is any conceptual mistake in my code:
module bram_dual(...
0
votes
1
answer
306
views
Updating signals sequentially in VHDL
I am a current student looking for some knowledge on VHDL. I understand that VHDL is a concurrent language. I've learned that you are able to update signals sequentially using a process statement. I ...
- 9
-1
votes
1
answer
211
views
how can i get the fullpath to a file named bigfifo.sv using tcl to querty the project file?
In vivado how can I get the fullpath to a file named bigfifo.sv?
When I run get_files at the TCL prompt, it just prints a long list of the fullpath of all the files in my project.
- 6,771
1
vote
0
answers
108
views
FROM_DEVICE DMA Request hangs Linux on multi CPU server motherboard
I am developing FPGA based PCI Express (PCIe) device that should work under Linux OS, so I am writing the Linux kernel driver also. One of the features of the device is that it can write data to Linux ...
- 66
-2
votes
2
answers
122
views
Elementwise array mutliplication in VHDL
How can I multiply two arrays elementwise.
In Matlab, I could do
a[1:6 ] = b[2:7] .* b[1:6]
I have tried
calc_imag(5 to 7) <= i_real(5 to 7) * i_real(6 to 8);
but it doesn't seem to work
- 37
0
votes
1
answer
160
views
Odd Number Detector on FPGA
Implement a circuit that illuminates an LED when an odd number of the eight slide switches are set to “1”.
This is the project that I am trying. Only one solution came to my mind without using ...
- 23
0
votes
1
answer
71
views
Why does the Inferred Latch error occur during the synthesis process?
I think I've written all the cases for switch and if, but I don't understand why following message occur in synthesis process.
warnings messages
This module performs the operation of converting BCD ...
- 15
0
votes
1
answer
85
views
Difference between combinatoric signal dependant on clocked signal vs. registering it
I'm currently writing some VHDL code for a FPGA where a done signal is set through a state machine.
The fsm feeds data into a shiftregister and asserts 'done' when it's complete.
Now there are two ...
- 3
2
votes
1
answer
188
views
What is the granularity of the AXI-ACE protocol?
I'm working on an embedded FPGA-CPU system (Xilinx Ultrascale+ Zynq Board) with a cache-coherent CPU and an optionally coherent FPGA. The FPGA uses the AXI4 protocol, with the additional ability to ...
- 637
0
votes
1
answer
405
views
Restricting Verilog parameters
I am writing a simple Verilog module, that needs to have restrictions on its parameter values. By that I mean only certain values are allowed to be assigned to a generic parameter. I know this could ...
- 13
0
votes
2
answers
318
views
How can I compare the arrays in VHDL?
I am having problem with comparing the arrays in VHDL,
in SysVerilog language it is easy but I couldn't find any solutions for my problem can you help me please ?
It says it is illegal to use other =&...
0
votes
1
answer
245
views
Can't get Mealy FSM simulation working after synthesis
I am trying to design a non-overlapping sequence detector according to the following state-machine:
I wrote the following code, in systemverilog:
typedef enum { S0, S1, S2, S3 } State;
module ass26(
...
- 270
3
votes
1
answer
789
views
Vitis HLS Pointer to Pointer is not supported for variable when initializing struct array
I'm trying to make a state machine that is synthesizable into a hardware description through Vitis HLS. I'm getting the error ERROR: [HLS 214-134] in function 'kernel1(char*, int)': Pointer to pointer ...
- 1,237
0
votes
1
answer
544
views
Rocketchip: make failing under /emulator and /vcs due to "mill: command not found"
Discussed in https://github.com/chipsalliance/rocket-chip/discussions/3492
Originally posted by AnuragMalwee September 20, 2023
Hi, I am building the rocket-chip project for the first time, and never ...
1
vote
1
answer
1k
views
4x16 decoder using 2x4 decoders not working correctly
I'm currently working on a Verilog project where I'm attempting to run a testbench for a 4x16 decoder using a 2x4 decoder. However, I'm encountering problems with the output. I've provided the code ...
0
votes
2
answers
191
views
SystemVerilog inheritance, aggregated classes and parent function call
I have a problem with super.func() call in SV.
I have three main classes:
class_C extends class_B;
class_B extends class_A;
class_A;
And I have three configuration (aggregate) classes:
inner_C extends ...
0
votes
1
answer
130
views
How do I adapt the `ap_uint` type so it can be used in a union?
#ifndef _ENTRY
#define _ENTRY
#include <cstdint>
#include "ap_int.h"
struct US0 {
ap_uint<1> tag;
union {
struct {
ap_uint<2l> v0;
} ...
- 4,112
0
votes
1
answer
164
views
sbt test does not work and all the tests fail
I have installed rocket-chip and it needs chisel to compile i have also downloaded chisel , but when i run sbt test all the tests fail, am i doing something wrong . is there an alternative for sbt ...
- 3
-2
votes
2
answers
207
views
Assign a Output into Two Modules in Verilog
In the below Verilog Code, I want to assign my outputs into two modules namely two_input_checker and three_input_checker. But when I assigned them directly as shown as below, it gives a error.
module ...
0
votes
1
answer
869
views
FPGA DSP: how to calculate the noise floor level
I have a FPGA DSP module that detect the pulse based on the threshold of the noise floor level. My module run the incoming IQ signal to a Xilinx CORDIC-Vector Translate module to produce phase and ...
- 13
0
votes
1
answer
400
views
VHDL Ping Pong Game on Cyclone IV EP4CE22 - Display Not Updating Correctly
I'm trying to implement a Ping Pong game using VHDL on a Cyclone IV FPGA (EP4CE22) with ModelSim as my simulation tool. I have the basic game logic implemented, but I'm facing an issue with the ...
user19026118
-1
votes
1
answer
2k
views
Yocto bitbake ERROR: quilt-native-0.66-r0 do_configure
My FPGA based design is based on Vivado 2020.2 and Yocto running on Ubuntu 2020.04.6 LTS. I have FPGA design A that builds successfully .bit and .xsa files successfully without any critical warnings ...
- 1
0
votes
2
answers
1k
views
Why even use std_logic instead of std_ulogic for implantation purposes?
I know that std_logic is resolved subtype of std_ulogic and allows you to drive a signal by multiple sources.
If I understand correctly, designs that contain multiple drivers cannot be implemented ...
- 1
-2
votes
1
answer
895
views
How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?
I insert a verilog file into another verilog file by using "`include "
And when I used the synplify script(*.tcl) to try to synthesize, one error occured:
invalid command name "+incdir+&...
- 27