2,824 questions
-1
votes
1
answer
238
views
having trouble adding reset button to verilog code
I have a top module that implements a 14-bit counter.
I added an input button in the top module and to the 14-bit counter
In the counter I check to see if the button is pressed and if so reset the ...
- 65
1
vote
0
answers
279
views
RISC-V in FPGA's booting is stucked with "Starting kernel..." when i changed the version of linux Kernel
I tried to implement RISC-V in VC707 boards with vivado-risc-v(https://github.com/eugene-tarassov/vivado-risc-v) within different version of original code.
First of all, I checked it works well when i ...
- 11
-1
votes
1
answer
2k
views
Create a pulse of a given signal
I have a signal sig. This may remain high for multiple clock cycles. I want to create a pulse of it that should toggle for as many clock cycles for which the signal was high.
That is every time my ...
- 145
1
vote
0
answers
169
views
How to know the maximum local memory size that can be used in FPGA kernel (using oneAPI SYCL or OpenCL)?
There is a big difference between the document provided through the vendor document and the program output, and I don't quite understand how the local memory is used in the FPGA.
The FPGA I am using ...
- 11
0
votes
0
answers
103
views
TSL2591 I2C protocol : sensor returning register number instead of valid data
as part of my academy project I am writing i2c protocol in system Verilog in VIVADO on FPGA PYNQ Z2.
after completed all code and pass simulation, connected the TSL2591 device.
according to ILA ...
- 1
0
votes
1
answer
258
views
(VHDL-1154) near 'std_logic_vector' ; type conversion expects one single argument
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.ALL;
use ieee.math_real.all;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
port
(
signal Led_7 ...
2
votes
0
answers
144
views
Does PicoBlaze have separate flags for each regbank (like Z80), or are the same flags used in both regbanks?
Does PicoBlaze have separate flags for each regbank (like Z80), or are the same flags used in both regbanks? For instance, consider the following code:
regbank a
load s0, 0
sub s0, 0
regbank b
load ...
- 840
0
votes
1
answer
235
views
indexing memory for UART transmission using > 100% SLICEs Tang Nano
I am trying to build a simple UART reception parser command line based on example from Tang Nano 9K repo here, here is my modified version. It basically uses a memory to hold some values, which is ...
- 105
0
votes
1
answer
151
views
frequency counter with Lattice ice40 dev board
Hello I am very new to the FPGAs.
My goal is to make a frequency counter that would be able to count 5-6Mhz with +-5Hz error.
Would Lattice ICE40 be sufficient for this task?
This board looks pretty ...
- 1
0
votes
1
answer
185
views
Can't add description of customization parameters in Edit Packaged IP of Xilinx Vivado
Settings: Vivado 2023.1 on Windows 10.
The customization parameters were added after Create and Package New IP wizard. The Description field of all the newly added customization parameters is always ...
- 7
1
vote
1
answer
77
views
Elements in the array are not updated at the same time in post-implementation timing simulation
I am trying to write a FSM. A very simple one, which updates its value (0 to 4 and then 0 again) on the posedge of the input SCL.
This is my design source code:
`timescale 1ns / 1ps
module fsm(
...
- 11
0
votes
0
answers
108
views
Function Wash not increasing value in sec signal in VHDL
I'm very new to VHDL and for my digital design project I have to make a simulation of a washing machine in a DE10-Lite FPGA with finite states.
Everything seems good so far but when it's turn for the ...
- 27
0
votes
1
answer
453
views
How to read data from FPGA on HPS side
I am a novice. I have a cyclone V board. I have generated several 32-bit ASCII codes through verilog on the FPGA side. I want to send them to the HPS side through the H2F AXI bus and program the HPS ...
- 11
1
vote
1
answer
476
views
Code for an adjustable countdown timer that can be set to different countdown values
My code isn't running .
It is Verilog code for an adjustable countdown timer that can be set to different countdown values: 1000 seconds to 0 seconds, 500 seconds to 0 seconds, 60 seconds to 0 seconds,...
- 11
2
votes
1
answer
196
views
How to deal with ActiveLow Reset / change implicit clock frequency?
How to config implicit clock from 100MHz to 50 MHz(So its show up in my WaveGTK Sim)?
How to deal with Active Low / Active High?
ex.
val io = IO(new Bundle() {
val activeLowReset = Input(Bool())....
- 21
0
votes
1
answer
725
views
How to calculate Setup slack and Hold slack?
I'm having trouble understanding how to calculate Setup slack and Hold slack correctly. According to the Intel Quartus Timing Analysis manual, Setup slack is calculated as Data Required Time (Setup) ...
1
vote
1
answer
83
views
Carry look ahead adder fails in generating proper sum and carry bits
Full adder module:
`timescale 1ns / 1ps
module FA(A,B,carry_in,sum,carry_out);
input A,B, carry_in;
output sum, carry_out;
assign sum = A ^ B ^ carry_in;
assign carry_out = (A^B) | ((carry_in) & (...
0
votes
0
answers
161
views
Why does state instantly go to last state whenever pushbutton is pressed
I am implementing a door lock that requires user password. I have implemented states to identify predefined passwords of 123, 122, and 121, and it unlocks the door after the correct password is ...
- 11
1
vote
1
answer
264
views
Multiple drivers conflict for unknown reason
I'm working on a 4-bit divider using subtractors. It works fine on my testbench, but when I use it in my project and do "apio build," I get the following warnings:
Warning: multiple ...
0
votes
1
answer
416
views
FPGA Max 10 DE10 Lite Board Error (169026) on Quartus 22.1 VHDL
I am trying to implement the project https://www.youtube.com/watch?v=50EC76bpkQI
When I try to compile the Quartus II, it gives me the following errors:
Error (169026): Pin myLEDR[1] with I/O standard ...
- 21
1
vote
2
answers
225
views
Full Adder output always set to X
I am starting in FPGA coding, and one of my first exercises is to code a full adder. I am using SystemVerilog to code within Vivado. My take on this is as follow:
Source:
`timescale 1ns/10ps
module ...
- 163
2
votes
2
answers
141
views
Why does my VHDL countdown timer on Nexys3 FPGA board switch between 59 and 68?
I created a 60 second countdown timer in VHDL and connected it to the 7-seg displays on a nexys3 FPGA boar but it doesn't work. This is a project for my college class.
I'm not really skilled at VHDL ...
1
vote
1
answer
526
views
Why am I receiving the wrong bits when sending data through UART on Basys3 FPGA?
My goal is to send data from my Basys3 board to my laptop, and I am using UART to do so. The Verilog code I wrote successfully sends data to my computer, but I am receiving the wrong bits.
Below you ...
- 37
2
votes
1
answer
459
views
Module that converts ASCII to 7-segment display using FPGA
I have a question about the meaning of having a begin statement for each letter. Why is it necessary or is it? Also, what does the HexSeg[x] = y mean for the letters with a begin statement? I am ...
- 25
1
vote
2
answers
1k
views
How to Read Data from a specific address of the FPGA QSPI Flash board?
I'm new to Vitis and XilinX-edk world.
I'm working on a project and i want to implement a design that uses microblaze to do these 3 tasks :
1-Read some data from a specific QSPI Flash address.
2-Save ...
0
votes
1
answer
89
views
What value do uninitialized internal signals take on when when used in signal assignment?
In the following code, A is attached to I/O while B is an internal signal that is not assigned an initial value.
architecture Behavioral of adder is
signal B : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
...
- 9
1
vote
0
answers
89
views
memory initialization with riscv32 ASM
I want to initialize memory block of riscv32 x'10000000 to x'10002000 with 0 to 2048 and variable "key" will take the value from address x'10000400 as the pass word. Because of optimization ...
- 91
0
votes
2
answers
498
views
How to split code and data into 2 different ELF files?
I have a code for an embedded microncontroller in an FPGA that contains variables stored in the stack and I would like to seperate the code from those variables and put those into 2 ELF files. The ...
- 1
0
votes
1
answer
126
views
non-blocking assignments with if statements
A bit confused about how Verilog interprets this code block and how it is synthesized in FPGA.
...
data_reg[bit_count] <= rx;
bit_count <= bit_count + 1;
if (bit_count == 7) begin
bit_count &...
- 41
1
vote
1
answer
78
views
Variable does not update in module
I'm trying to write a simple Verilog module and a testbench for it on intel's Quartus Prime and checkout it's waveform on Questa FPGA simulator.
The code basically has a clock and a 4-bit counter. The ...
0
votes
2
answers
571
views
CLOCK_DEDICATED_ROUTE error in creating an RS latch
I am trying to describe a RS asynchronous latch in VHDL. I receive this error from vivado.
[Place 30-574] Poor placement for routing between an IO pin and BUFG.
If this sub optimal condition is ...
1
vote
1
answer
235
views
Vexriscv - implement ram as block ram
How can I generate a Vexriscv core in a way that the generated ram is a vendor specific block ram (e.g. Intel/Altera or Xilinx)?
I tried it by using the black boxing possibility (see https://spinalhdl....
user7063051
0
votes
1
answer
600
views
Altera Quartus II Can't synthesize current design -- Top partition does not contain any logic
I've started working with FPGAs and VHDL
In Model Sim everthing works and does what it has to do, but if I want to compile it in Quartus the error shows up.
library ieee;
use ieee.std_logic_1164.all;
...
- 1
1
vote
1
answer
651
views
How to get access to Xilinx FPGA temperature in hdl code?
I'm using a Xilinx ultrascale FPGA (specifically, AXKU-040). A project I'm involved in requires real-time monitoring of FPGA temperatures. I need to read the temperature of the FPAG and send it to the ...
0
votes
1
answer
195
views
Can synthesizers pay attention to intentional 'Z' at compile time?
In Verilog, I have an input port that I would like to make optional. It's the start pin for a microarchitecture. If user does not want to drive the start pin manually, the module will use its own ...
- 869
0
votes
1
answer
295
views
How to use XADC's GPIO on Xilinx KC705 FPGA
I output the clock generated through GPIO, but I cannot check the data on the oscilloscope.
I am developing using the AMD Kintex7 FPGA KC705 Evaluation Kit and using the Vivado 2022.2 version.
I want ...
- 31
0
votes
1
answer
78
views
couldn't implement registers for assignments on this clock edge(VHDL)
``--! start state logic
start_int <= start;
ssl_edge_detect_proc: process(start_int,clk)
begin
if rising edge(start_int) then
start_edge_old<='1';
else
start_edge_old<='0';
...
- 1
0
votes
1
answer
276
views
Yosys optimizes GPIO RX module away
I recently started playing with the iE40 icestick evaluation board. I encountered what
I think is strange behavior:
It seems that Yosys wants to optimizes away a module which takes a port connected to ...
-1
votes
1
answer
120
views
HLS : Cellular Automata
So I have been trying to build the following, using Vitis HLS:
ca.hpp:
#include <cstdio>
#include <cinttypes>
#include "ap_axi_sdata.h"
#include "hls_stream.h"
#...
- 298
0
votes
1
answer
600
views
FFT IP Core - the results of Matlab and FFT IP Core didn't match?
I asked this while back in Xilinx Forum but I got no help, still need the help that's why am asking here.
I am working on FFT IP Core to match its result with Matlab. I created an RTL Kernel(XO) using ...
- 175
0
votes
1
answer
2k
views
Clocking Block Cycle Delay Problem in SystemVerilog
I have a stuck Clocking Block in SystemVerilog that i try to understand but I could not. I have just a normal Clocking Block like this, and I just drive one signal to understand.
`timescale 1ns/100ps
...
0
votes
1
answer
215
views
STA of 2 clocks with the same frequency
Imagine a design has 2 input clocks. They have the "same" nominal frequency but originate from 2 different sources and therefore are asynchronous to each other.
The clocks are defined as ...
- 179
-1
votes
1
answer
152
views
PYNQ Z2 : Arduino PINS and HC SR04
My team mates and I have tried to estimate a distance using the captor HC SR04 (Ultrasonic captor) on PYNQ Z2 board.
We are using the Arduino_IO library.
GND -> GND
VCC -> 5V
TRIG -> AR1
ECHO ...
- 1
-2
votes
1
answer
1k
views
How not to write "always@(posedge clk) and always@(negedge clk)" in one module
I learn "Do not mix negedge posedge for the same clock in one module (synthesis is possible, but analysis is difficult)"
"So chat gpt
always @(posedge clk)
...
always @(negedge clk)
...
- 1
0
votes
1
answer
516
views
Using keyword `all` in a sensitivity list of a clocked VHDL process
I would like to present the following two versions of VHDL code for a flip flop.
Clock and reset in the sensitivity list of the clocked process:
library ieee;
use ieee.std_logic_1164.all;
entity ...
- 45
0
votes
2
answers
536
views
How setup- and hold times affect the functionality of the FPGA implementation?
I am currently working on a VHDL module that first reads in the given input data in parallel via a shift register and then outputs the stored data bit by bit at the output in each clock cycle. For ...
2
votes
1
answer
120
views
SPI - SCLK stuck in mid transmission
Context:
An SPI bus is being used to communicate the iMX8 with an FPGA. After some configuration commands, the FPGA begins to fill a memory. When this memory is full, the iMX8 is notified and sends a ...
- 41
0
votes
1
answer
183
views
Trying to find an error in my VHDL Code, with no luck
There is syntax error that I cannot understand.
process(clk) on line 166 of the code the error showing up is Error: Syntax error near 'process' , i'm pretty sure i've checked the code before this ...
- 29
0
votes
0
answers
149
views
How to write in a block memory in vivado
In order to display an image from fpga ZedBoard to the screen through VGA interface, I created a dual block memory to store an image and read it from that memory to display it. I dont know how to ...
0
votes
1
answer
646
views
Division in Verilog and Q factor representation
I am currently working on a design of an algorithm for signal processing.
I created a model in software that appears to work fine and I am now trying to translate it to verilog.
Below is what I do in ...
- 848