493 questions
-2
votes
0
answers
21
views
Unique ID registers in HPS (ARM) side of Cyclone V
I need to uniquely identify individual devices at runtime from the HPS (ARM Cortex-A9) side.
Does the HPS side of the Cyclone V SoC have any built-in unique ID registers, such as:
- A hardware serial ...
0
votes
0
answers
60
views
How to fix State <name> contains multiple transitions, but more than one transition equation are TRUE when <text> in Quartus?
I'm trying to develop a Elevator FSM machine in quartus in order to get his equivalent to HDL code. The FSM is this:
But when I set the Input, transitions and output in "State Machine Wizard&...
- 71
1
vote
0
answers
118
views
mSGDMA interaction via linux-socfpga on Agilex 5
I am trying to use this DMA driver to transfer memory from a streaming device to SDRAM.
This is my design in Qsys/Platform designer:
The design streams a predictable pattern of 6x6x6x6x to SDRAM.
The ...
- 23
1
vote
1
answer
100
views
Using Quartus IP Catalog, how can I get predefined module name and ports order?
For the code below, I utilized a predefined RAM module from Quartus to create the RAM. How do I determine the port order when instantiating it?
I understand it must be compatible with the module from ...
- 11
0
votes
1
answer
346
views
What's the difference between a constant and an inline constant in Vivado?
I'm currently working on a simple project on an FPGA and wanted to set an enable-input to 1. Now when using the built in IPs for a constant, two components show up. One is "Constant" and the ...
- 13
2
votes
1
answer
62
views
Timer countdown starts from wrong value on initial start but works correctly afterward
I'm working on a Verilog project where I have implemented a countdown timer using preset counters. However, I'm encountering a strange issue when I set a time and start the countdown. On the initial ...
- 21
-1
votes
1
answer
106
views
modelsim can't find object (vish-4014) and i it doesn't show any wave so that can i add it to scope
this is my code for a fun Fire extinguishing system in a 50 unit apartment.this is fire_detection_system.v:
module fire_detection_system (
input wire clk, // Clock signal
input wire reset, // ...
- 1
0
votes
1
answer
104
views
VHDL internal signal assignment does not work
I'm a newbie in VHDL Programming and I am having trouble with this VHDL code (sync counter). The variable Q_AUX_4 is never assigned to the output Q_OUT because when I try to run simulation, using ...
1
vote
1
answer
130
views
Verilog module always going to default case when assigning value to input
I'm just starting to use Verilog. One of my first projects has been a module that controls 4 7-segment displays with a 16-bit input. My BCDtoSSeg module is the following:
module BCDtoSSeg (BCD, SSeg);
...
- 37
1
vote
1
answer
58
views
What is "strictly control signal" and Why is its input unconstrained?
This is from book "STA for nanometer design"
This section describes the constraints for the input paths. The
important point to note here is that STA cannot check any timing on a
path that ...
- 115
1
vote
1
answer
115
views
Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand
I am getting error at line 59. I tried to Google it, but I couldn't find anything. Here is my code:
always @(posedge clk or negedge nReset) begin
if (minute_start_in == 1'b1) begin
...
- 29
0
votes
1
answer
661
views
How to add IP Libraries to Questa with Cocotb?
I am trying to simulate a test bench for an Intel IP (AVST CDC) in Questa using cocotb. What would be the correct way to add generated simulation files to run in cocotb?
I've generated IP Simulation ...
-1
votes
1
answer
180
views
Fibonacci LFSR using the Altera Megafunction LPM_SHIFTREG - how to initialise? [VHDL]
I am having a frustrating time designing a linear feedback shift register where there is a need to use Altera's LPM's, in this case the LPM_SHIFTREG. This must be used as I have an assignment and exam ...
- 21
1
vote
1
answer
169
views
ModelSim Issue - Discrepancy of Data Output Results from ModelSim versus Altera's VWF Editor
I am instantiating two components within a top level file, where this implements a Phase Accumulator and LUT with an 8-bit FTW, to essentially create a simple DDS system. Mind you this is very ...
- 21
1
vote
1
answer
460
views
Analyzing synchronizer MTBF in Quartus
I have a message from Quartus that it found synchronizer chains, but is unable to perform MTBF analysis on them. Yet, nothing is really explained in the manuals except how to recognize synchronizers ...
- 22.7k
0
votes
1
answer
51
views
dpcc code for fpga emulation using jupyter notebooks
I was performing emulation of hough transform for FPGA's on Jupyterlab but then all i had to do was run the cells:
I get the following error ->
u196294 is performing Hough Transform compilation ...
0
votes
1
answer
453
views
How to read data from FPGA on HPS side
I am a novice. I have a cyclone V board. I have generated several 32-bit ASCII codes through verilog on the FPGA side. I want to send them to the HPS side through the H2F AXI bus and program the HPS ...
- 11
-2
votes
1
answer
137
views
Timing diagram of convst. signal of ADC (ads8556) [closed]
I want to work on ADC (ads8556). In Figure 3 In the Parallel Read Access Timing Diagram, when the conversion time (tconv) finishes, and during the acquisition time (tACQ), there are multiple ...
1
vote
1
answer
663
views
Error: object on left-hand side of assignment must have a net type
I am new to working with Verilog, and I was given some code that implements uart. I think it might be missing something since I am getting the compiling error shown below:
Error (10219): Verilog HDL ...
- 415
0
votes
2
answers
571
views
CLOCK_DEDICATED_ROUTE error in creating an RS latch
I am trying to describe a RS asynchronous latch in VHDL. I receive this error from vivado.
[Place 30-574] Poor placement for routing between an IO pin and BUFG.
If this sub optimal condition is ...
0
votes
1
answer
132
views
View report.html after DPC++ compilation for FPGA on DevCloud connected with Jupyter
I already got report.html (optimization report), but don't known how to view it.
I tried complete command "firefox repotr.html" and expecting open it by web browser Firefox, but got:
Command ...
- 111
1
vote
1
answer
2k
views
Output 'X' instead of '1' or '0' in VHDL
I am working on a code convertor using multiplexors and I am facing issues when testing it on ModelSim. Basically it outputs X where there should output 1.
I found out that the error may be where I ...
- 51
-1
votes
1
answer
126
views
communication between PC and Altera through RS232 cable using VHDL and C#
I'm doing a school project where I need to pass notes (char, ascii) using a C# code in VS to an Altera card using a RS232 cable. when I'm sending a single note('A') the data goes through just fine but ...
- 1
3
votes
1
answer
1k
views
How to connect module to module in Verilog?
I am a beginner in the development of FPGA. I am interested in how to correctly combine several modules in the top-level file.
For example: in the top-level file, I want to connect the output of ...
- 33
0
votes
1
answer
402
views
How to correctly calculate the frequency of the device in Timing Analyzer, Intel Quartus
I have 3 modules: modulo remainder generator, modulo adder and modulo Wallace adder. Their speeds are related as follows: remainder_modulo > wallace_adder_modulo > modulo_adder. But Timing ...
0
votes
1
answer
464
views
Error running 'make DETECT_DEVICES' on Intel FPGA Monitor Program
I'm currently trying to run ARM assembly on my DE series board. However when I try to open my project I get the following error on the Intel FPGA Monitor Program:
Error running 'make DETECT_DEVICES'. ...
- 144
-1
votes
1
answer
4k
views
Verilog - output exuals to XXXXXXXX
I'm trying to design a 32-bit ALU. While simulating using Modelsim output R becomes mixed with x's and 0's like this, at time=20 the addition is calculated and at time=40, substraction is calcualted.
...
- 47
-1
votes
1
answer
420
views
Quartus-FPGA: Disable Path Optimization
module path1(out, in, w0, w1, w2, w3, w4, w5, w6, w7, w8, w9);
input in;
output out;
output w0, w1, w2, w3, w4, w5, w6, w7, w8, w9;
not(w0, in);
not(w1, w0);
not(w2, w1);
not(w3, w2);
not(w4, w3);
...
- 633
1
vote
1
answer
477
views
SV code: if statement inside always_comb construct does not infer purely combinational logic
I cannot figure out the solution to this error, and the only other answer I find online for the same error is this
I have been stuck on this problem for a while and I feel like I am going in circles. ...
- 11
0
votes
1
answer
428
views
(vcom-1339) Case statement choices cover only 6 out of 10 cases
Case statement choices cover only 6 out of 10 cases for my vending machine code I am getting this error after execution of my very long program in VHDL. However its said that When others => can be ...
0
votes
1
answer
327
views
How do I load an FPGA's Registers with Data?
Note this question is not for when I am simulating. I have found numerous resources as to how to use readmemh which does not solve my problem. What I am trying to do is load the RAM for a processor ...
-1
votes
1
answer
562
views
How can I prevent that DSP blocks are synthesized away if they are not connected to a top level output?
I am using an Intel Stratix 10 FPGA and Quartus Prime Pro 21.4 to develop a power test project.
I cannot figure out how keep Quartus from optimizing away my DSP blocks.
I want to use all 3000 DSP ...
-1
votes
1
answer
817
views
Error (10028): Can't resolve multiple constant drivers and Error (10029): Constant driver
I am new to Verilog, and trying to write a traffic light code where the LED light changes after certain time. I'm keep getting on different errors while compiling. I tried to fix them by changing the ...
- 13
0
votes
1
answer
173
views
Result on FPGA in Intel DevCloud
I am learning OneAPI OpenCL FPGA implementation in the Intel DevCloud by following this link (https://github.com/intel/FPGA-Devcloud/tree/master/main/QuickStartGuides/OpenCL_Program_PAC_Quicksta...). ...
0
votes
1
answer
746
views
NIOSII Softcore UART Interrupt
I try to get an UART IP core in combination with the NIOS2 (softcore) running on the Cyclone 10 LP evaluation board.
So far everything works fine in polling mode. However, I cannot manage to get the ...
user7063051
0
votes
1
answer
526
views
NIOSII with Remote System Update IP Core for Cyclone10LP does not execute
I am working on an update procedure for the Cyclone10LP FPGA with Quartus Prime 20.1.1.
The platform design is done the following.
The NIOSII Software Build tool for Eclipse Project is configured ...
user7063051
0
votes
1
answer
857
views
"Serial Loader Device is missing" during Convert Programming File with Quartus Prime
I try to convert multiple SRAM object (.sof) files to one JTAG indirect configuration file (.jic) using Quartus Prime, however I always receive the following error message.
Serial Flash Loader device ...
user7063051
0
votes
2
answers
289
views
How do i get a 100kbps clock for an I2C on Quartus Prime?
I am doing a university project in which i have to build a I2C which have only one slave and will have to transmit a data with 5 bits, 4 bits for the number which is in the range of 0 to 9 and 1 bit ...
0
votes
1
answer
118
views
niosii processor Altera C program
I'm currently working on the Altera DE0 board with the QuartusII Web Edition software. I need to use a nios processor on Qsys to display a shifted signal from a GPIO pin on my board. The input signal ...
- 1
2
votes
1
answer
158
views
port SYCL/DPC++ code originally written for GPUs to FPGAs
I'm kinda new to the world of FPGAs and I'm trying to port some code written for GPUs to FPGAs, to compare the performances.
From my understanding, using parallel_for ain't a good practice (in fact it ...
- 335
0
votes
0
answers
86
views
Parallel for is very slow compared to iterative solution
I am trying to accelerate an algorithm using DPC++. What happens is that the normal calculations takes 1.5 times faster than kernel parallel execution. The following code is for both calculations.
the ...
1
vote
1
answer
1k
views
Verilog/SystemVerilog: passing a slice of an unpacked array to a module
I am using a DE10-Nano with Quartus Prime to try to implement the following.
I have two modules: Module1 and Module2. Module1 declares a RAM like this:
reg [15:0] RAM[0:24576];
// init RAM 0:8191 with ...
0
votes
2
answers
146
views
OpenCL FPGA: Kernel Execution of 2 copies of same kernel is not being made in parallel. In addition to that, there is also idle time in between them
My goal is to complete FFTs of 2 - 4K Data points together. Hence, I made 2 kernel objects from the same kernel and Enqueued the tasks at once, i.e. without any Buffer Read-Write or any callbacks in ...
0
votes
1
answer
194
views
Getting nan values from OpenCL FFT kernel on FPGA
I was trying to use the Intel's FFT1D kernel by writing the Host program by my own for Intel FPGA. Link to Intel's FFT1d can be found here
I have also given my host program below, wherein, I have a ...
3
votes
1
answer
260
views
Design of compression using OpenCL FPGA
I am working on a lossy compressor, and I am wondering which way is more suitable for the design, the first one is to transfer data to the global memory until all the data is processed and the second ...
- 54
0
votes
0
answers
408
views
How to use fpga-arria10-passive-serial driver in Linux?
I have a board that has an NXP iMX8M-Plus processor and an Intel Arria 10 GX FPGA on it.
I want to configure the FPGA using the iMX8M-Plus processor through passive serial interface of the FPGA. I use ...
- 1,794
1
vote
0
answers
232
views
Flashing a Cyclone IV's SROM chip via its JTAG connection
Is there an inbuilt or pre-existing feature I can use to accomplish Flashing a Cyclone IV's(EP4CE6E22C8) SROM(W25Q16BV) chip via its JTAG connection? Maybe some setting when compiling in Quartus to ...
0
votes
1
answer
1k
views
I am getting error when check my systemverilog code in quartus II
I have this simple code checked with Quartus II. First, It gives me error 5000 iterations for loop limit then I try to change verilog constant loop limit variable in settings and now it is giving me ...
- 53
-1
votes
1
answer
437
views
Compilation of verilog code in quartus prime takes much longer after adding block
I am attempting to make the snake game in verilog using my DEE-10 Lite and compiling using Quartus Prime (Lite Edition Version 20.1.1).
The Analysis and Synthesis time takes almost 10 times longer ...
- 1
-1
votes
1
answer
271
views
The clock speed is two times faster when the clock duty cycle is 50%
I want to generate 102Hz clock on a FPGA board(the one with cyclone 3）
the original clock on the hardware is 50MHz, so I divided it by 490196 to get 102Hz clock
but the clock speed is two times faster ...
- 13