775 questions
2
votes
1
answer
82
views
Not seeing one-cycle delay for register in Modelsim
My register doesn't work properly. The output changes simultaneously with the input. There should be a one-cycle delay, but I am not seeing it from the simulation in Modelsim. Does anyone know why?
...
- 61
6
votes
1
answer
119
views
Deallocating after returning line using std.textio ieee library
A known problem in VHDL is that using parts of a return statement (e.g to_string(slv(i))'length) will generate a warning/error on compile. To work around an unknown string length, I tried using the ...
- 131
0
votes
2
answers
154
views
Generating a PWM signal in Verilog (Quartus Prime Lite)
I'm trying to generate a pulse width modulated signal to control the power with duty cycle, but don't know where I went wrong
This is the verilog code
module pwm_generator (
input wire clk, ...
- 73
0
votes
1
answer
115
views
Shifter's vectors (VHDL) stay undefined in Modelsim . What is wrong?
Sadly, stack wont let me post an image yet...so,for uni i have to recreate a circuit in vhdl code, but when i run it simulate it in Modelsim, all vectors (except input_vector) remain undefined. I get ...
- 17
-1
votes
1
answer
75
views
Intel FGPA ModelSim Error: Invalid time string
I have been working on my desktop using Quartus prime lite and ModelSim, but recently I got a weird error that I can't seem to fix. I have tried restarting my pc, uninstalling and reinstalling Quartus ...
- 1
2
votes
1
answer
60
views
Weird Behavior of buffers in modelsim simulation
I ran into a problem that buffer in my simulation does not work as I expected.
I tried some test and got the following results.
I created code in Verilog that generates two buffers in different ways:
...
-2
votes
1
answer
163
views
Error using a VHDL function inside package into a systemverilog module. Mixed VHDL - SystemVerilog -mixedsvvh example
I present the VHDL & SystemVerilog code, of a very simple example.
I would like to know if it's possible to do what I am trying. And in case it is, why I am getting an error Considered I am using ...
- 9
-1
votes
1
answer
106
views
modelsim can't find object (vish-4014) and i it doesn't show any wave so that can i add it to scope
this is my code for a fun Fire extinguishing system in a 50 unit apartment.this is fire_detection_system.v:
module fire_detection_system (
input wire clk, // Clock signal
input wire reset, // ...
- 1
-1
votes
1
answer
68
views
How to make modelsim run #10 in ns in testbenches?
I'm trying to run a test bench in which the inputs change every 10 ns, so I used command #10 in the testbench code. However, in the wave form, it appears to change every 10 ps.
How can I change it?
- 125
0
votes
1
answer
1k
views
How to simulate Xilinx IP-cores in Modelsim?
I have Vivado 2016.4 and Modelsim 2021.3 installed. My Vivado project contains Xilinx ip-cores. I want to model everything in Modelsim. It is useless to choose the Modelsim simulator in the simulation ...
0
votes
1
answer
203
views
Verilog always @(posedge clk) doesn't work
I want to introduce a one-cycle delay to valid_dat by using @(posedge clk) but it doesn't work. The counter works fine with the clock and increases by one every clock cycle. But valid_delay changes ...
- 61
1
vote
1
answer
53
views
SystemVerilog not reading data correctly
The data read from A_arr, B_arr and C_arr are incorrect.
The value I have in Moddelsim is not what I defined in the testbench.
I have a testbench for my design. It should fetch inputs from A_arr and ...
- 61
-1
votes
1
answer
59
views
Why does the s2 signal have the opposite value as the s3 signal after the nanosecond 20?
I have this code in VHDL:
library IEEE;
use IEEE.std_logic_1164.all;
entity crono is
end entity crono;
architecture crono of crono is
signal x1, x2, x3, s1, s2, s3, s4: std_logic;
begin
x1 &...
- 1
0
votes
1
answer
142
views
What is wrong with the array constant declaration in my VHDL code?
I am a digital technology student trying to learn VHDL.
I wrote this testbench code for 4 bit bcd adder to 7 segment display
I have tried all the possibilities i and chat GPT could think of but the ...
0
votes
1
answer
98
views
How to cast a macro using the streaming operator
I have Systemverilog macros for endianess-aware parsing of unpacked data:
The purpose of this macro is to take any BYTE_WIDTH Bytes from an BYTE_OFFSET offset at a Byte array, and pack them into a ...
0
votes
1
answer
104
views
VHDL internal signal assignment does not work
I'm a newbie in VHDL Programming and I am having trouble with this VHDL code (sync counter). The variable Q_AUX_4 is never assigned to the output Q_OUT because when I try to run simulation, using ...
0
votes
1
answer
270
views
How to provide a status to questa vsim on detected test harness issue?
I had existing test benches with icarus verilog. I am exploring questa. The test benches can be called individually or batched. With icarus it provides an extension to have a non-zero return code. ...
- 22.7k
-1
votes
1
answer
142
views
Modelsim error flag in integer wrapping around - change to vhdl code not possible
I have an old VHDL code which I need to run a simulation for with Modelsim. This code "includes" a warp around condition which is of no consequence in real hardware but fails in simulation.
...
-1
votes
2
answers
112
views
How do i add a "for" loop in VHDL
I'm trying to make this "for" loop work but im stuck with the same error: "Illegal concurrent statement".
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ...
- 1
3
votes
1
answer
411
views
How do I create a testbench for my Verilog code?
I am trying to print the graph of this in Modelsim with Verilog
This is the code I wrote in Modelsim:
module circuit (
input A,
input B,
input C,
input D,
output reg F
);
always @* begin
F = ~(~A &...
- 31
0
votes
1
answer
209
views
How can I avoid glitches in behavioural vhdl code simulations? [closed]
I've been trying to write VHDL code for a counter.
Ultimately, I would like to take the output value, check it with a constant value, and see if the counter has reached the constant value. if it ...
-1
votes
1
answer
679
views
Questasim tool showing error after updating code and re running for schematic
Problem related to Model Sim Questa tool. (System verilog)
I have run the code in Questa Sim, then check the schematic of that verilog code.
But again I changed something in that code and try to run ...
0
votes
1
answer
192
views
Modelsim displays unknown or garbage number in transcript
I'm trying to write a testbench to test my processor using the $display() statement.
But I don't know why there are unexpected, there is unexpected or garbage numbers printed on the transcript.
This ...
- 11
0
votes
1
answer
212
views
Why is Modelsim displaying "Error: MIF contains illegal character" when I try to simulate?
I'm currently designing a MIPS based processors in VHDL using Quartus 20.1 along with Modelsim 2020.1.
I created a MIF file that (hopefully) calculates the GCD of a given number. My MIF file consists ...
- 1
1
vote
1
answer
169
views
ModelSim Issue - Discrepancy of Data Output Results from ModelSim versus Altera's VWF Editor
I am instantiating two components within a top level file, where this implements a Phase Accumulator and LUT with an 8-bit FTW, to essentially create a simple DDS system. Mind you this is very ...
- 21
-1
votes
1
answer
172
views
modelsim wave is empty and msg displays "xxx"
I am running a verilog file on Modelsim, however the wave area is empty and displays a "xxxxxx" message. I am very new to Verilog/Modelsim/Quartus in general, any help would be greatly ...
0
votes
1
answer
166
views
VHDL concurrent assertions and delta cycles
I am trying to use VHDL concurrent assertions in order to verify that a signal correctly drives another. As they should be directly connected at some times (no latching), I want to use a concurrent ...
- 1
0
votes
1
answer
86
views
What is the reason for this error in ModelSim for my Verilog code? (string_literal.v(3): near ";": Syntax error.)
module string_l();
string a;
initial
begin
a="Hello";
$display ("@%gns a=%s", $time, a);
end
endmodule
- 163
1
vote
1
answer
445
views
When I simulate my counter in Modelsim, the outputs are undefined
I've made counter in Quartus as schematic file. Then generated Verilog design file from that scheme. I was able to configure and run simulation in Modelsim, but outputs of counter (Q0..Q3) always ...
- 27
1
vote
1
answer
360
views
$fopen returns the MCD, but the MCD does not work
I'm trying to open a file and write stuff, simple. My implementation is not so simple.
I'm using Verilog/SystemVerilog and Modelsim on the Windows OS. My command line in Modelsim is:
set generics &...
- 40
0
votes
1
answer
125
views
16-bit ALU: try to change operation code, but results still remain the same
I am trying to write a 16-bit ALU. I have compiled everything successfully, but when the operation code alu_code changes, the result C stays the same (the first operation result).
Here's my code for ...
1
vote
1
answer
1k
views
4x16 decoder using 2x4 decoders not working correctly
I'm currently working on a Verilog project where I'm attempting to run a testbench for a 4x16 decoder using a 2x4 decoder. However, I'm encountering problems with the output. I've provided the code ...
0
votes
2
answers
191
views
SystemVerilog inheritance, aggregated classes and parent function call
I have a problem with super.func() call in SV.
I have three main classes:
class_C extends class_B;
class_B extends class_A;
class_A;
And I have three configuration (aggregate) classes:
inner_C extends ...
0
votes
1
answer
400
views
VHDL Ping Pong Game on Cyclone IV EP4CE22 - Display Not Updating Correctly
I'm trying to implement a Ping Pong game using VHDL on a Cyclone IV FPGA (EP4CE22) with ModelSim as my simulation tool. I have the basic game logic implemented, but I'm facing an issue with the ...
user19026118
-1
votes
1
answer
508
views
How to show enumeration value of variable, rather than the bit vector value in ModelSim
I'm currently working on a final project for my Verilog course, which involves building a processor. As part of the project, I've implemented a state machine to manage different stages of the ...
2
votes
2
answers
129
views
How can I stop the simulation at stop bit for I2C master code?
I am trying to write Verilog code for I2C master, and there are a couple of problems I am facing. I was able to compile and run its testbench on Quartus and modelsim, respectively. However, I am ...
- 21
-1
votes
1
answer
5k
views
ModelSim Install in Ubuntu 22.04 [closed]
I am using Ubuntu 22.04 LTS as my OS system. I need to install modelSim for participating Verilog or HDL . But I am failed to do it. How to Install ModelSim in Ubuntu 22.04 ? Is there any terminal ...
1
vote
2
answers
258
views
Strange error in ModelSim but not in Quartus?
I'm doing a Verilog project on quartus, and when I do the analysis and synthesis, quartus doesn't give me any errors.
When instead I try to compile the files on ModelSim, it gives me the following ...
- 13
1
vote
1
answer
292
views
Error with Multiply-Accumulation Verilog Simulation: Illegal output or inout port connection
I'm trying to build a Multiply-Accumulator (MAC) module for Matrix Multiplier with Verilog.
Here's Verilog Code for the MAC module:
module Multiply_Accumulation(MAC_out, sel, a, b, clk, rstn); //...
- 11
1
vote
2
answers
184
views
Why does this Verilog module output x even though it has non-X inputs?
I am trying to create a 4-bit ripple carry adder using 4 full adders each comprised of two half-adders.
This is the code for my half-adder:
module HA (input a, b,
output reg cout,
output reg ...
- 79
0
votes
1
answer
78
views
couldn't implement registers for assignments on this clock edge(VHDL)
``--! start state logic
start_int <= start;
ssl_edge_detect_proc: process(start_int,clk)
begin
if rising edge(start_int) then
start_edge_old<='1';
else
start_edge_old<='0';
...
- 1
2
votes
1
answer
281
views
Simulation mismatch when using shortreal + shortrealtobits + bitstoshortreal combination in modelsim tool
Here is the minimal reproducible problem:
file: top.sv
module top(input [31:0] in1, output [31:0] out1);
assign out1 = in1;
endmodule
file top_tb.sv
module top_tb;
shortreal in1_real;
shortreal ...
- 404
1
vote
2
answers
652
views
Verilog's display function is giving an incorrect output?
I spent quite a long time debugging some Verilog code only to realize that the design was correct the entire time and for whatever reason Verilog's display function was having unexpected behavior.
I ...
- 1,777
1
vote
2
answers
849
views
How to access signals in submodules with multiple modules?
I have the following Verilog file named main.v:
module m1(input a, b, output wire c);
assign c = a & b;
endmodule
module main(input x, y, output wire z);
wire k;
m1 m1_inst(.a(x), .b(y), .c(k))...
- 411
2
votes
1
answer
166
views
How to correct this error "Illegal reference to net q"? [duplicate]
I am getting this error when I am compiling my file which Using Behaviour Modelling is designing a positive edge triggered T-Flip-Flop with asynchronous clear in Verilog code.
module t_flip_flop (...
- 23
0
votes
0
answers
109
views
How to find minimum of n sfixed array values using VHDL
I need to find the minimum of 5 s-fixed values, as I have an array of 5 values val3=[x1 x2 x3 x4 x5]
and I need to fill another array val33=[y1 y2 y3 y4 y5], while y1 is the minimum value of the array ...
- 11
1
vote
1
answer
509
views
Why do I get a syntax error for omitting a semicolon after one #10, but it is not needed for others? [duplicate]
My friend wrote an FSM code that generates 3 numbers (1,4,1) in binary.
The code works and compiles in modelsim.
I wrote a testbench for it so I can simulate it.
The testbench code errors in line 24 ...
- 5
2
votes
2
answers
2k
views
Random number generator using $dist_uniform in SystemVerilog
I am trying to generate a random number using the $dist_uniform using Quartus and ModelSim.
The relevant code section is as follows (within a loop):
rand= $dist_uniform(10,20,25);
rand_test=$random;
'...
- 55
-1
votes
1
answer
778
views
Modelsim 2021.4 (Windows): How to exclude files from code coverage report
I am trying to exclude certain vhdl files from my code coverage report, but I can't get it to work. My report always shows all available files.
My workflow is as follows:
in Modelsim I compile the ...
- 21
-1
votes
1
answer
658
views
QUESTA + Modelsim using using command Gate Level Simulation
I have installed Quartus V20 + ModelSim V20. It's the first time I use that. I have buyed a book to try to understand how to simulate / use a FPGA system.
I have done a simple cirtuit to check the ...
- 1,717