775 questions
35
votes
2
answers
4k
views
vsim does not accept -modelsimini parameter on Windows
I'm using the command line argument -modelsimini <modelsim.ini> to specify my own modelsim.ini file for most QuestaSim / ModelSim executables.
This works perfectly fine on Linux for vcom and ...
- 16.5k
25
votes
3
answers
126k
views
What is the difference between Verilog ! and ~?
So it ended up that the bug that had kept me on for days, was a section of code that should have evaluated to False evaluating to True. My initial code went something like:
if(~x && ~y) begin
...
- 1,228
17
votes
3
answers
27k
views
How does signal assignment work in a process?
I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here:
...
signal x,y,z : bit;
...
process (y)
begin
x<=y;
z<=...
- 16.9k
16
votes
9
answers
26k
views
The font of my modelsim is too small to see
As you can see, the font of modelsim's text editor is very small. But I can't change the size in Tools->Edit Preferences->Source Window->Fonts.
However, I can make the letters bigger by set the DPI ...
- 333
15
votes
2
answers
14k
views
Where can I find a definitive list of the ModelSim error codes?
I am running some VHDL through ModelSim. Each error and warning has its own error code (like this: (vcom-1292) Slice range direction "downto" specified in slice with prefix of unknown direction. This ...
- 3,730
13
votes
3
answers
17k
views
Wait until <signal>=1 never true in VHDL simulation
Below is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? The console output is simply GOT HERE. It never gets to the line GOT HERE 2. I would think ...
- 3,465
12
votes
1
answer
6k
views
Is there a way to toggle leaf names in ModelSim through the TCL API?
I am looking for a way to toggle leaf names of the nets in ModelSim view, in GUI mode. In other words, an equivalent of pressing "Toggle leaf names <-> full names" button:
I am aware of the way of ...
user405725
11
votes
1
answer
29k
views
How to open Modelsim project files
I can open Modelsim project files by doing File->Recent Projects. However I do not know any other way to open projects. If I use File->Open it only opens up individual files, not projects. How can ...
- 56k
9
votes
2
answers
6k
views
Configure ModelSim simulation to display text
Can I make ModelSim simulation to display text (rather than a numeric value) on a signal? I have a couple of state-machine states say,
localparam S_IDLE = 2'b00;
localparam S_START = 2'b01;
...
- 1,228
9
votes
1
answer
4k
views
Altera Quartus falsly says Modelsim isn't installed
Installed Quartus 13.0 with Modelsim in Fedora 22 64-bit. Running Quartus in 32-bit because I get lots and lots of problems otherwise. However, I can start Quartus, create a project, synthesize it, ...
- 5,073
8
votes
2
answers
18k
views
ModelSim-Altera error
I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch ...
- 2,916
7
votes
2
answers
3k
views
Detect timescale in System Verilog
How do I detect the timescale precision used in a simulation from the source code ?.
Consider I have a configuration parameter(cfg_delay_i) of some delay value given by user in timeunits as fs .If the ...
- 337
7
votes
1
answer
2k
views
Quartus II use file only in simulation
I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component ...
- 662
6
votes
2
answers
3k
views
VHDL test results into jUnit (or other Jenkins-recognized) format
I'm setting up automated regression testing for an FPGA project, almost exactly as described here:
Continuous integration of complex reconfigurable systems
Now I want to get test results (from VHDL ...
- 286k
6
votes
1
answer
119
views
Deallocating after returning line using std.textio ieee library
A known problem in VHDL is that using parts of a return statement (e.g to_string(slv(i))'length) will generate a warning/error on compile. To work around an unknown string length, I tried using the ...
- 131
6
votes
1
answer
5k
views
Finding when a certain signal has a particular value in Modelsim using tcl
I'm trying to speed up debugging. In a large trace I'm search for particular values of a signal. Im using QuestaSim 10.0b under linux.
I already found out that can be done in Modelsim/QuestaSim with ...
- 4,796
6
votes
3
answers
17k
views
How can I read binary data in VHDL/modelsim whithout using special binary formats
I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and an combined entity + architecture file. I want to read the ethernet frames that the testbench will send to ...
- 836
6
votes
1
answer
12k
views
VCD dump for vhdl simulation via modelsim. HOWTO?
It's the first time i try to generate a VCD and i am getting some troubles.
I have a testbench called bench_minimips.vhdl that contain the entity sim_minimips.
I want simulate it and get a VCD out of ...
- 4,041
6
votes
4
answers
10k
views
Testing VHDL / FPGA Using Python and A Simulator [closed]
The standard way to test VHDL code logic is to write a test bench in VHDL and utilize a simulator like ModelSim; which, I have done numerous times.
I have heard that instead of writing test benches ...
- 69
5
votes
7
answers
2k
views
verilog modelsim fpga
Sorry for Newbish question.
I am trying to learn about FPGA programming.
Before I spend $1K on a FPGA board:
if I just want to learn Verilog, can I run it entirely in Modelsim? (I realize there are ...
- 43.1k
5
votes
3
answers
38k
views
Power function in vhdl
I want to make power function using vhdl where the power is floating number and the number is integer (will be always "2").
2^ some floating number.
I use ieee library and (fixed_float_types.all, ...
- 409
5
votes
2
answers
6k
views
ModelSim Message Viewer Empty
I'm currently using Modelsim 10.1 alongside ISE 13.4 and run a very simple test bench. All code is VHDL.
I ran into trouble using VHDL's assert statement the other day: Errors and warnings are output ...
- 4,131
5
votes
2
answers
5k
views
Procedure call in loop with non-static signal name
In some testbench code I use a procedure to do something with a signal. I then use this procedure multiple times in sequence on different signals. This works fine as long as I explicitly define the ...
- 1,905
5
votes
1
answer
2k
views
Cocotb VHDL need for FLI
I am currently setting up a Cocotb based verification environment.
I just discovered that the example provided with Cocotb don't work in my case if using VHDL, because my simulator has no FLI (...
- 369
5
votes
1
answer
12k
views
How to concatenate strings with integer in report statement?
I'm having trouble getting the following report statement to work:
report "ERROR: instruction address '" & CONV_INTEGER(a(7 downto 2)) & "' out of memory range." severity failure;
Where a is ...
- 29.1k
5
votes
2
answers
7k
views
ModelSim error: Instantiation of 'OR' failed
I am having trouble with running a Verilog project with ModelSim Student Edition 10.2c. Everything compiles without error, however I get the following error at runtime:
# vsim -gui work.testbench
# ...
- 16.2k
5
votes
2
answers
13k
views
Weak 'H', Pullup on inout bidirectional signal in simulation
Is there a way to tell the simulator (I'm using Modelsim) to pull a signal to weak 'H' when it's not being driven by either bidirectional interface?
For example if I have an I2C signal I2C_SDA that ...
- 3,465
5
votes
3
answers
3k
views
Modelsim and GHDL cannot dump vhdl user-defined signal types into vcd?
I'm trying to dump internal signals from a simulation executed either by modelsim or ghdl. Everything works fine using:
For modelsim, add vhdl sources, and compile all then:
vsim -novopt work....
- 606
5
votes
2
answers
28k
views
Why ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0?
Why does Modelsim complain about the component instantiation i1?
Time: 0 ps Iteration: 1 Instance: /vhdl2_uppgift_1_extra_vhd_tst/i1
** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, ...
5
votes
1
answer
2k
views
Modelsim VHDL Array Initialization gives warning (vcom-1320)
I'm using Modelsim's VHDL-Compiler (vcom) for code linting with SublimeText (VHDL 2008). While initializing an array of standard_logic_vector I get the following warning:
vcom: warning Warning - (...
- 51
5
votes
2
answers
5k
views
modelsim: find processes/variables
I would like to write a nice function that adds signals and process variables to the wave. While it's quite easy with signals, I don't know how to do it with variables. I would expect something like "...
- 644
5
votes
1
answer
2k
views
The globally static error (modelsim vs quartus)
This simple test leads to an error while compiling with modelsim whereas Quartus is fine to go through the whole synthesis/fitter process.
library ieee;
use ieee.std_logic_1164.all;
entity submodule ...
- 1,456
5
votes
0
answers
805
views
Scons for FPGA? [closed]
Is there somebody who has used 'Scons' as a replacement for 'make' for quite large FPGA projects?
Did it ran out-of-the-box or is there still some hacking to be done for the VHDL or Verilog language? ...
- 1,373
4
votes
3
answers
10k
views
How can I make Modelsim exit with a specified exit code from SystemVerilog
I am trying to build a test bench in SystemVerilog using a clocking block cb_module.
I am running Modelsim from the command line:
vsim -c test_bench -do "run -all"
Everything works fine but I can ...
- 972
4
votes
5
answers
4k
views
How to wait for Modelsim Simulations to complete before proceeding in TCL script
I am trying to execute a regression test in Modelsim. I call a TCL script which compiles my source files and launches vsim. I launch a .do file and it runs a series of testbenches which all output ...
- 61
4
votes
6
answers
47k
views
Debugging Iteration Limit error in VHDL Modelsim
I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it:
Error: (vsim-3601) Iteration limit reached at time 400 ps.
I'm not sure what it means, but I've ...
- 51
4
votes
2
answers
24k
views
Bit slicing in verilog
How can I write wdata[((8*j)+7) : (8*i)] = $random; in verilog programming language? , where i and j are reg type variable. Modelsim gives error for constant range variable. How could I write it in ...
- 89
4
votes
1
answer
5k
views
How to execute 'Zoom Fit' in ModelSim/QuestaSim from TCL console?
I'm using ModelSim / Questa-SIM from command line in GUI mode. If ModelSim runs in GUI mode I would like to execute a 'Zoom Fit' from my imported 'wave.do' file.
I pass this file to vsim by -do wave....
- 16.5k
4
votes
1
answer
6k
views
Ambiguous type in infix expression VHDL
I'm getting the following error in ModelSim:
Error: [..]/test1_toVectorAlignment_rtl.vhd(40): Ambiguous type in infix expression; t_RAMXx8 or ieee.std_logic_1164.STD_LOGIC_VECTOR.
ARCHITECTURE rtl ...
- 1,863
4
votes
2
answers
438
views
Shifter output is always 0 when using concatenation and case
I have the following code:
module shifter(
input[7:0] in,
input[1:0] amt,
output logic[7:0] out
);
always_comb case(amt)
2'h0: out = in;
2'h1: out = {{in[6:0]}, 0};
2'h2: out ...
- 1,738
4
votes
1
answer
2k
views
VHDL integer range inclusive? Difference in FPGA vs. simulation
I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand.
I have a 50MHz clock source.
I have a signal defined as:
SIGNAL ledCounter : integer range 0 to ...
- 521
4
votes
2
answers
14k
views
(Tcl?) Script for running modelsim with testbench as parameter from shell
I want to make a script, which can be executed from shell like:
./myscript -test1 or tclsh myscript.tcl -test1
I want it to open ModelSim, compile units, load a desired testbench, run simulation. ...
- 384
4
votes
3
answers
14k
views
How to restart a Verilog simulation in Modelsim
I'm trying to debug a Verilog module. I find it tedious to have to stop a simulation, modify code, and then go through the process of starting the simulation again. Is there an easier way?
- 33.3k
4
votes
2
answers
2k
views
VHDL - Why does using the length attribute directly on a function produce a warning?
I have a VHDL function that returns a std_logic_vector representation of a record and I want the length of that std_logic_vector. I am able to use the length attribute directly on the function. Why ...
- 43
4
votes
1
answer
7k
views
Is default value required for a Verilog parameter declaration?
Parameters in Verilog code is usually declared with a default value, like:
parameter UP = 1;
But if the parameters is always to be overridden at module instantiation, then I have also seen ...
- 6,061
4
votes
1
answer
4k
views
Using VHDL Record in SystemVerilog Testbench in Modelsim
I've done research on this, but the examples that I've found on other web pages have broken links. I'm looking for an example of how to import a custom VHDL record that is contained in a package into ...
- 3,465
4
votes
1
answer
961
views
get dependencies of vhdl entity in modelsim
I compiled a large VHDL design in ModelSim successfully. The design is not important here, my question is about ModelSim commands for any VHDL design.
Now let's say I have an entity E1 there and I ...
- 4,449
4
votes
2
answers
3k
views
With ModelSim, how to update waveforms to the newest dataset?
Background : ModelSim v10.4d installed with quartus v16.0
I wrote a .do file to simulate my design with ModelSim.
The steps in my .do file are:
1- vcom *.vhd : compile all sources files and ...
- 419
4
votes
1
answer
283
views
Modelsim signal declaration issue
With Modelsim I would like to test a code but one signal always remains uninitialized. Here a code snipped to explain the problem with Modelsim:
-- Signal Declaration
signal shifter : ...
- 225
3
votes
10
answers
24k
views
Reset modelsim editor to the default one
I want to reset my editor to the default one in Modelsim but I don't know how.
When I double click on a project it opens in Notepad. I tried to change the value of the editor variable from the "Edit ...
- 96