445 questions
0
votes
0
answers
54
views
Verilog & Vivado - How to load memory initialization files into BRAM on post-synthesis simulations
I am designing a 16 bit microcontroller for a college project using Vivado and Verilog. On behavioral simulations i use $readmemh and everything runs fine, the instructions are loaded from memory and ...
1
vote
1
answer
99
views
Should UVM testbench work with pre-synthesis or post-synthesis FPGA code? [closed]
I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow.
Should I develop my ...
- 139
2
votes
2
answers
169
views
In Vivado, what is "[Synth 8-7213] Expression condition using operand 'x' does not match with the corresponding edges used in event control" error?
When I am doing some development with Verilog and Vivado, I wrote some Verilog code as follows:
module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED);
always @(posedge clk or ...
- 78
0
votes
0
answers
89
views
What is the .tcl command for Cadence Genus to disable scan chain while synthesizing the RTL Design
When I'm placing a Standard I/O Cell in Cadence Innovus, Tool is throwing an error as your design contains scan chains, so I want to disable the scan chain while performing synthesis of Design in ...
1
vote
2
answers
115
views
Is Verilog with variable as a bitselect/bitslice synthesizable?
Is the following Verilog code always synthesizable?
I'm trying to use a variable as a bit select into a multibit variable:
`define MaxSize 5
wire[(`MaxSize-1):0] myVect;
wire myBit;
...
- 11
0
votes
2
answers
102
views
SystemVerilog intermediate top output signal
I am wondering which SystemVerilog coding fits better for ASIC/FPGA Synthesis/linting. I mean for simulation/synthesis/... purpose if it makes any difference and if a coding style is preferred, for ...
- 35
0
votes
1
answer
257
views
TCL Script for Including Date and Time in Top Module of Design Sources in Vivado
I’m trying to write a TCL script in Vivado 2021.2 that dynamically includes the current date and time in my top module by fetching the name and path of the top module.
The following TCL command works ...
- 11
1
vote
1
answer
67
views
Binary - BCD convertor works in sim, but does not work on FPGA
I defined a binary to BCD converter to use on a Basys 3 development board. In simulation, the results are as expected, and it follows the timing exactly.
I included the BCD converter in a top module, ...
- 35
0
votes
0
answers
87
views
How can I transform yosys gate primitives (e.g. $reduce_or) to simple gates and then pattern match those to more complex Verilog cells?
I am new to Yosys, and I want to optimize arbitrary netlists to a set of complex cells.
For example's sake, let's consider an or-reductions:
red_or3x1_test.v
module test (A, Y);
input [6:0] A;
...
- 11
0
votes
0
answers
191
views
How is division ("/" operator) synthesized in verilog?
I have seen some mixed answers for whether or not the division operator "/" could be synthesized for constant values that are not a power of 2 so I went ahead and tried it using Synopsys ...
- 11
-1
votes
1
answer
137
views
synthesizable encoder (non-priority) using system verilog for loop
I have a table of 16 entries where each entry is 4 bits wide. There is a 4 bit input search vector that i have to find in the table and then return the row number of the matched entry. The entries are ...
- 1
-2
votes
1
answer
154
views
Mismatch between behavioral simulation and post-synthesis functional simulation in vivado
I am writing a VHDL module to convert an incoming stream via axi stream (tdata, tvalid, tready and tlast) with tdata's with 8 bits such that the fist 4 bytes are registered in the output port A of 32 ...
- 57
0
votes
1
answer
261
views
How can I execute a primetime command through a perl script
I am converting a TCL script to perl.
I have tried it using the system command and back tics. I am executing the perl script in primetime in the following way,
exec script.pl.
The script contains many ...
- 1
3
votes
2
answers
218
views
Does Verilog automatically convert Behavioral modeling into Structural modeling?
I'm a junior Electronic Engineering student currently learning Verilog. I've been studying various modeling methods in Verilog, including Structural, Dataflow, and Behavioral modeling. I have a ...
- 33
1
vote
1
answer
85
views
4-bit counter that increments after every second: simulation always shows xxxx at the output
Here's my code:
//`timescale 1ns / 1ps
module FourBitLedToggle(
input res,
input Clk,
output [3:0] led
);
reg [27:0] count;//for 1 second check
reg clk1s;//1 second clock
...
0
votes
1
answer
137
views
Synthesis ERROR: [Synth 8-27] else clause after check for clock not supported
I'm trying to build a clock divider based on integer counters. the simulation works correctly but the synthesis fails with the error above and marks line 25.
I want the clocks to be reset only for one ...
- 13
-1
votes
1
answer
534
views
how to write a library file
I'm trying to learn synthesizing with yosys.Im working with verilog now.
I know we need a library file for it, and I have written a .v file for it. how do I convert this into a .lib file? In other ...
0
votes
2
answers
140
views
How to connect combo code to a module's interface modport?
Inside my top level SystemVerilog module is an instance, (rd_blk), that has an interface modport, (sec_rd). I need to temporarily connect it to combinational code, but I'm having difficulty coming up ...
- 15
1
vote
2
answers
662
views
Xilinx Vivado schematic for if else statements
I am learning SystemVerilog. While coding, the synthesis schematic for the following if statements don't make sense to me.
module ifelseDUT(
input logic sela, selb, selc, da,db,dc,
output logic dout
...
- 131
1
vote
1
answer
70
views
Does the synthesis flow always require writing a wrapper? If so, where do the signals that we use as inputs come from?
I understand what it means when we say we write a wrapper of an RTL code block, that is to create an interface of it with the rest. My question is, when I do synthesis, I also need to write a wrapper ...
- 11
1
vote
1
answer
340
views
Incremental synthesis with yosys
For a multi-file Verilog project using Yosys for synthesis, the script would generally look something like the following:
# read the all files
read_verilog *.v
# synthesis
synth -top
# output ...
- 25
-2
votes
1
answer
500
views
Why does running Synthesis take the same amount of time every time with Quartus, Vivado and Libero?
With all FPGA tools I have used so far: Intel Quartus Prime, Xilinx Vivado, Microsemi Libero SoC, it always takes the same amount of time whenever I run synthesis. What I would expect is that the ...
- 708
0
votes
1
answer
99
views
2d array structure flattened into registers?
In my verilog code I have an array declaration such that:
reg [8:0] mem [1024:0] ;
In the procedural block, I have this
always @(posedge clk)
for (i = 0; i < 8; i=i+1) begin
...
0
votes
1
answer
144
views
When designing digital circuits, which is more power efficient, an if-statement or a multiplication (particular case)?
I'm currently writing the code of a hardware accelerator in Verilog 2001, and a question has arisen to which I could not find an answer (maybe I don't know how to search for it):
There's a simple ...
0
votes
2
answers
267
views
Synthesis error in Vivado: [Synth 8-3380] loop condition does not converge after 2000 iterations
module Delay_Module (
input wire clk,
input wire [3:0] data_in,
input wire [7:0] delay_cycles,
output reg [3:0] output_data
);
reg [4:0] counter = 0;
reg [3:0] memory [0:47];
integer i;
...
1
vote
1
answer
538
views
Parameterizable FIFO with multiple inputs and outputs?
I want to create a FIFO with multiple & parameterizable number of inputs and outputs. Saying as soon as there are enough data, the FIFO will pump them out. In my use case, I have 4 inputs and ...
- 65
1
vote
1
answer
329
views
Post-synthesis simulation error: unable to find ports due to flattening 2D array ports to 1D
In post-synthesis simulation on Vivado, the netlist flattens a 2D array to a 1D array. How can we adapt the testbench to the change of these ports? For example in DUT instantiation, feeding values to ...
- 11
0
votes
1
answer
525
views
What is the basis for setting parameter values in the sdc file?
Recently, I did some rtl practice like divider and sequence detector. I used the same sdc file to synthesis and it comes from an open source project.(Project link) The following codes come from the ...
- 95
-2
votes
1
answer
895
views
How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?
I insert a verilog file into another verilog file by using "`include "
And when I used the synplify script(*.tcl) to try to synthesize, one error occured:
invalid command name "+incdir+&...
- 27
2
votes
1
answer
281
views
How to know whether a Verilog code can be synthesized?
I want to figure out whether Verilog syntax can be synthesized by doing practice. The RTL code is shown below:
module CRC10 (Clock, Data_In, CRC_En, CRC_Clr, CRC_Out);
input Clock;
input CRC_En;
input ...
- 95
0
votes
1
answer
606
views
Vivado won't synthesize BRAM, making LUT instead
After adding the line number_of_lines <= ram[0], Vivado won't synthesize a BRAM component. Instead I got a LUT scheme.
module bram3 (clka,clkb,ena,enb,wea,web,addra,dia,dib,doa,dob,rst);
...
- 29
-1
votes
2
answers
488
views
Vivado linter: inferred latch for signal 'out_reg'
I am new to Verilog. I want to write a simple module to do clock dividing without using PLL. The module is named "uart_brg" since I plan to use it later in an uart module for exercise ...
- 1,241
1
vote
1
answer
270
views
Flip flop reset with ternary operator instead of if-else statement
I am wondering if it is OK to replace flip flop resets with the ternary operator to minimize line count and improve readability. Does the RTL below have the same effect in simulation and synthesis?
...
- 181
0
votes
1
answer
2k
views
Setting values in an initial block in Verilog
I think I may be mis-understanding how the initial block works in Verilog.
I have the following bit of code driving hardware sprites:
// horizontal and vertical screen position of letters
logic signed ...
- 759
0
votes
1
answer
195
views
Can synthesizers pay attention to intentional 'Z' at compile time?
In Verilog, I have an input port that I would like to make optional. It's the start pin for a microarchitecture. If user does not want to drive the start pin manually, the module will use its own ...
- 869
3
votes
1
answer
464
views
How to make the data_flow control of a matrix multiplier synthesizable?
I have designed a matrix-vector multiplier with systolic array architecture. I finally got the simulation to work. Now that I want to synthesize the design it seems that the data_flow control block is ...
- 66
0
votes
1
answer
2k
views
Why my simulation and post synthesis simulation results are different in vivado?
I simulated the rtl code and got the desired output, but when I run the post synthesis functional simulation, I see some random signals in the simulator screen and getting wrong output.
This is my ...
0
votes
1
answer
1k
views
Vivado Not Creating Schematic after Synthesis
I am able to simulate my cpu with no errors and received the waveforms I expected. So I went to run the synthesis and I received my foreplaning, i/o planning, and etc. However it did not produce a ...
- 23
-1
votes
1
answer
162
views
Verilog: Simulation and Hardware Implementation differ in one state behaviour
I am currently trying to implement a UART-simulation into an FPGA. The idea is, to just cycle through predefined data (defined by byte_array_com_message_1 - 4) which will then be put out on one line (...
- 39
1
vote
1
answer
70
views
Variable output stream delay attempt not working
The module I'm trying to get working takes in a pulse data stream with pulses occurring between 500 and 12500 clk cycles, and it needs to delay the stream by a specified number of clk cycles between ...
1
vote
1
answer
124
views
Line 49: Assignment under multiple single edges is not supported for synthesis
I tried to change a variety of different issues like the begin-end statements but nothing seems to be working. I also tried changing the reg [3:0] to [7:0] since I was also getting some warnings
I'm ...
-2
votes
1
answer
161
views
What will this synthesize to in DC?
What will the be DC synthesis output? I don't have access to DC. If a=1 and b=1 will both address locations get updated ? Addr1 and addr2 are logic as well and guaranteed not to be equal.
logic [3:0][...
- 1
0
votes
1
answer
911
views
Start up behavior of moving average filter is different between pre and post synthesis functional simulation
I've implemented a moving average filter (in Verilog), based on an article I read which performs differently pre and post synthesis. The design implements $y[n]=y[n-1]+x[n]-x[N-1]$.
module ma_width #(...
- 248
2
votes
0
answers
180
views
Logical synthesis of decoder into standard logical cells
I have a decoder defined in verilog as:
module my_decoder(
input [3:0] in,
output reg[19:0] out
);
always@(*) begin
case (in)
4'd0: out= 20'd114912;
4'...
- 249
2
votes
0
answers
299
views
Handling very large vector in VHDL
Similiarly to the question asked here, I face issues managing very large vectors in FPGA, and nothing really helped in the previous topic. I have a 2^15 bits wide sample, I want to make something ...
- 21
1
vote
2
answers
898
views
Is it possible to see if vivado inferred blockram?
I have a following piece of code:
module cw305_reg_aes #(
parameter pADDR_WIDTH = 21,
parameter pBYTECNT_SIZE = 14,
parameter pPK_WIDTH = 800 // 800 * 8
)(
input wire ...
- 3,266
1
vote
1
answer
1k
views
How to invert a bit of a packed array
logic [4:0] count_zeros;
logic [2:0] id;
integer i;
logic [7:0] [15:0] vld;
always@*
begin
count_zeros = 5'b0;
for (i=0; i<2; i=i+1)
count_zeros = count_zeros + ~vld[id][i];
end
For an ...
- 13
1
vote
1
answer
2k
views
Is indexing into an array with a signal synthesizable in verilog?
Are there any problems with synthesizing the following?:
// Read entry
assign entry[7:0] = my_array[read_address[10:0]][7:0];
Where read_address is a signal being used to read my_array.
I'm used ...
- 3,697
1
vote
0
answers
878
views
How to include another file through LPF file in Lattice Diamond tool?
In Lattice Diamond FPGA synthesis tool, pin placement is specified through a LPF (extension .lpf) file.
However, only a single LPF file can be active at a time.
Is it possible to include another LPF ...
- 6,061
0
votes
1
answer
1k
views
I am getting error when check my systemverilog code in quartus II
I have this simple code checked with Quartus II. First, It gives me error 5000 iterations for loop limit then I try to change verilog constant loop limit variable in settings and now it is giving me ...
- 53